Arithmetic, Floating Point - Control Data 3100 Reference Manual

ARITHMETIC, FLOATING POINT
Operational Field Address Field Interpretation
*FAD.I
60
m.b FP addition to AO
*FSB.I
61
m.b FP subtraction from AQ
*FMU.I
62
m.b FP multiplication of AO
*FDV.I
63
m.b FP division of AQ
*Trapped instruction if the Floating Point/Double Precision (FP/DP) arithmetic option is not present.
GENERAL FLOATING POINT/DOUBLE PRECISION NOTE
Figure 7-5 illustrates operand format and bit allocations for floating point instructions. Refer to
the Floating Point section of Appendix B for additional floating point considerations and examples.
TRAPPED INSTRUCTION IF FPjDP ARITHMETIC OPTION IS NOT PRESENT
23 1 8 1 7 1 6 1 5 14
00
60
I
a
I
b
I
m
a
=
addressing mode designator
b
=
index register designator
b
m
=
storage address: M
=
m
+
(B )
(Approximate execution time:
14-16.8
J.lsec.) option present.
Instruction Description: Add the 48-bit operand located in addresses M and M
+
1 to (AQ).
The rounded and normalized sum is displayed in AQ.
Com ments: The higher order bits of E hold the portion of the operand that was shifted out of AQ
during exponent equalization.
Refer
to
Figure 7-5 for operand formats.
7-43
Rev. B