Interrupt; Interrupt Mask Register Bit Assignments - Control Data 3100 Reference Manual

INTERRUPT
Operation Field
Address Field Interpretation
77.50 INCL x Clear interrupt
77.52 SSIM
x Selectively set interrupt mask
77.53 SCIM
x Selectively clear interrupt mask
77.57 IAPR
Interrupt associated processor
77.71 SFPF
Set floating point fault
77.72
SBCD Set BCD fault
77.73 DINT
Disable interrupt control
77.74 EINT
Enable interrupt control
23 18 17 12 11 00
(Approximate execution time: 1.S
~sec.)
77 50
x
x
=
interrupt mask register codes
Instruction Description:
This instruction clears the interrupt faults defined by the mask
codes in Table 7-8. Note that only internal I/O channel interrupts are cleared by this
instruction.
TABLE 7-8. INTERRUPT MASK REGISTER BIT ASSIGNMENTS
Mask Bits
*
Mask Codes (x) Interrupt Conditions Represented
00 0001 I/O Channel 0 (includes interrupts gener-
01 0002 1 ated within the channel
02 0004 2 and external equipment
03 0010 3 interrupts)
04 0020
(Not used)
05 0040
(Not used)
06 0100 (Not used)
07
0200 (Not used)
OS
0400
Real-time clock
09 1000
Exponent overflow/underflow & BCD faults
10 2000
Arithmetic overflow & divide faults
11 4000
Search/Move completion
*Mask bits 00-03 represent internal and external I/O interrupts for all instructions except INCL.
7-65