User I/O Connector; Figure 26. Location And Pin Orientation Of The User I/O Connector; Table 19: User I/O Connector Pinout - VersaLogic Blackbird VL-EPU4562 Hardware Reference Manual

User I/O Connector

The figure below shows the location and pin orientation of the user I/O connector.

Figure 26. Location and Pin Orientation of the User I/O Connector

Table 19: User I/O Connector Pinout

Notes:
1.
This 3.3 V power goes off in sleep modes. The SPKR# uses this power as should the PLED#
(there is no requirement for PLED# to use this power, but the VL-CBR-4005B paddleboard does).
2.
This 3.3 V power can be turned on or off similar to the 3.3V power to the Mini Card via the FPGA
VL-EPU-4562/4462 Reference Manual
Pin Signal
1 +5 V
3 USB1_P
5 USB1_N
7 +5V
9 USB3_P
11 USB3_N
13 +3.3 V (Note 1)
15 SPKR#
17 PWR_BTN#
19 GND
21 I2C Clock
23 I2C Data
25 GND
27 GPIO1
29 GPIO3
31 GND
33 GPIO5
35 GPIO7
37 +3.3 V (Note 2)
39 ETH0 LED
VL-CBR-4005B Paddleboard
Pin Signal
2 GND
4 USB2_P
6 USB2_N
8 GND
10 USB4_P
12 USB4_N
14 GND
16 PLED#
18 RST_BTN#
20 GND
22 V_BATT
24 V_BATT RETURN
26 GND
28 GPIO2
30 GPIO4
32 GND
34 GPIO6
36 GPIO8
38 GND
40 ETH1 LED
57