User I/O Connector; Figure 16. Location And Pin Orientation Of The User I/O Connector - VersaLogic Blackbird VL-EPU4562 Hardware Reference Manual

User I/O Connector

The 40-pin user I/O connector incorporates the signals for the following:
Four USB ports

Eight GPIO lines (these are functionally muxed with six timer I/O signals per FPGA

registers). There are eight timer signals and they share digital I/Os 16-9. The eight GPIO
lines on the paddleboard each have an alternate mode, accessible using the FPGA's
AUXMODE1 register. Refer to the EPU-4562/4462 Programmer's Reference Manual for
more information on FPGA registers.
Three LEDs (two Ethernet link status LEDs and a programmable LED)

2
Two I C signals (clock and data)

Push-button power switch

Push-button reset switch

Speaker output

This connector uses IEC 61000-4-2-rated TVS components to help protect against ESD damage.
The following figure shows the location and pin orientation of the user I/O connector.

Figure 16. Location and Pin Orientation of the User I/O Connector

VL-EPU-4562/4462 Reference Manual
Multi-purpose I/O
38