DEC 7000 AXP Operation Manual page 119

Flash ROM
Flash-erasable programmable read-only memory, which can be bulk erased
and reprogrammed. The KN7AA and KA7AA processors use flash ROMs
to hold the console and diagnostic firmware. In addition, one flash ROM
holds initialization code that bootstraps the main console/diagnostic firm-
ware. It also holds flash ROM recovery code. See also SROM code and
Flash ROM recovery code.
Flash ROM recovery code (FRRC)
The minimum amount of code necessary for remote flash ROM recovery;
used if the console/diagnostic ROMs have become corrupted.
Gbus
The path between the processor and the console/diagnostic firmware and to
two UART chips. The Gbus has two lines, one to the console terminal and
one to the power supply.
Hardware restart parameter block (HWRPB)
A page-aligned data structure shared between the console and system soft-
ware; a critical resource during bootstraps, recovery from power failures,
and other restart situations.
Hose
The interconnect between the IOP module on the LSB bus and the inter-
face module on another bus, such as the DWLMA module on the XMI bus.
IOP module (I/O port module)
The LSB module that provides the interface from the LSB bus to I/O buses.
The IOP module has four ports to support up to four I/O channels. Each
channel is known as a "hose." The IOP module must be node 8 of the LSB.
Node 8 is dedicated as both the highest and lowest arbitration level; the
IOP usually arbitrates at the highest priority. Besides providing for I/O,
the IOP module also generates the clock signals for the LSB bus.
KA7AA CPU module (VAX 7000)
The LSB CPU module that uses the NVAX+ chip, a CMOS-4 implementa-
tion with a macropipelined design. An 8-Kbyte cache is part of the CPU
chip and a 4-Mbyte cache is implemented in RAMs. The KA7AA processor
supports writeback caching.
Glossary-5