T-Sgpio 1/2 Headers; Unit Identifi Cation Switch/Led - Supermicro X8DTN+-F-LR User Manual

T-SGPIO 1/2 Headers

Two SGPIO (Serial-Link General
Purpose Input/Output) headers are
located on the motherboard. These
headers support Serial_Link inter-
faces for onboard SATA connections.
See the table on the right for pin
defi nitions.
Unit Identifi cation Switch/LED
A Unit Identifi er switch (UID) and a
rear UID LED indicator (LE2) are lo-
cated next to LAN ports on the back
of the chassis. When the user pushes
the rear UID switch, the rear UID LED
(LE2) will be turned on. Push the UID
switch again to turn off the LED indi-
cator. The UID switch provides easy
identifi cation of a system unit that may
be in need of service. See the tables
on the right for more information.
P1 DIMM3A
P1 DIMM3B
FAN5
P1 DIMM3C
FAN6
P1 DIMM2A
P1 DIMM2B
PHY
P1 DIMM2C
P1 DIMM1A
P1 DIMM1B
P1 DIMM1C
ALWAYS POPULATE DIMMxA FIRST
CPU1
C
X8DTN+-F
Rev. 2.00
Slot6 PCI-E 2.0 x8 (In x16 Slot)
LAN CTRL
Slot5 PCI-E x4 (In x8 Slot)
Slot4 PCI-E 2.0 x8 (In x16 Slot)
JPB
JPG1
Slot3 PCI-E 2.0 x4 (In x8 Slot)
BMC CTRL
Slot2 PCI-E 2.0 x4 (In x8 Slot)
Slot0 PCI-U
JPL1
JWOR1
Pin#
1
3
5
7
PWR I2C
JPI2C1
FAN7
FAN7/CPU2 JPW1
JPP1
JPP0
CPU2
P2 DIMM1C
P2 DIMM1B
P2 DIMM1A
P2 DIMM2C
P2 DIMM2B
P2 DIMM2A
P2 DIMM3C
P2 DIMM3B
P2 DIMM3A
ALWAYS POPULATE DIMMxA FIRST
JI2C2
JI2C1
Intel IOH36
JBT1
JBAT1
COM2
JTPM1
IPMB
JWD JL1 USB10
3-31
Chapter 3: Installation
T-SGPIO
Pin Defi nitions
Defi nition Pin
NC 2 NC
Ground 4 Data
Load 6 Ground
CLK 8 NC
Note: NC= No Connection
UID Switch (UID)
Pin Defi nitions
Pin# Defi nition
1 Ground
2 Ground
3 Button In
4 Ground
UID LED (LE2)
Status
Color/State OS Status
Blue: On Windows OS
Blue: Linux OS
Blinking
A. T-SGPIO1
JPW2 JPW3
B. T-SGPIO2
C. UID Swtich/UID LED
A
T-SGPIO1
JP5 JP7
B
T-SGPIO2
USB4/5
BIOS
USB6/7
Intel ICH10R
South Bridge
FAN4
JWF1
Defi nition
Unit Identifi ed
Unit Identifi ed