Chipset Overview - Supermicro X8DTN+-F-LR User Manual

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Chipset Overview

Built upon the functionality and the capability of the Intel 5520 platform, the
X8DTN+-F/X8DTN+-F-LR motherboard provides the performance and feature sets
required for dual-processor-based high-end systems and HPC/Cluster servers.
The 5520 platform consists of the 5500/5600 Series (LGA 1366) processor, the
5520 (IOH), and the ICH10R (South Bridge). With the Intel QuickPath interconnect
(QPI) controller built in, the 5500/5600 Series Processor is the fi rst dual-process-
ing platform that offers the next generation point-to-point system interconnect
interface which will greatly enhance system performance by utilizing serial link
interconnections, allowing for increased bandwidth and scalability.
The IOH connects to each processor through an independent QuickPath Intercon-
nect (QPI) link. Each link consists of 20 pairs of unidirectional differential lanes
for data transmission in addition to a differential forwarded clock. A full-width QPI
link pair provides 84 signals. Each processor supports two QuickPath links, one
going to the other processor and the other to the 5520 IO Hub.
The 5520 chipset supports up to 36 PCI Express Gen2 lanes, peer-to-peer read
and write transactions. The ICH10R provides up to six PCI-Express ports, six
SATA ports and eight USB connections.
In addition, the 5520 chipset also offers a wide range of RAS (Reliability, Avail-
ability and Serviceability) features. These features include memory interface ECC,
x4/x8 Single Device Data Correction (SDDC), Cyclic Redundancy Check (CRC),
parity protection, out-of-band register access via SMBus, memory mirroring, and
Hot-plug support on the PCI-Express Interface.
Main Features of the 5500/5600 Series Processor and the
5520 Chipset
•
Four processor cores in each processor with 8MB shared cache among cores
•
Two full-width Intel QuickPath interconnect (QPI) links, up to 6.4 GT/s of data
transfer rate in each direction
•
Virtualization Technology, Integrated Management Engine supported
•
Point-to-point cache coherent interconnect, Fast/narrow unidirectional links, and
Concurrent bi-directional traffi c
•
Error detection via CRC and Error correction via Link level retry
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Chapter 2: Overview