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5.2 I/O Address Map
The system chip set implements a number of registers in I/O address space. These registers occupy
the following map in the I/O space.
Address Range
0000 - 000F
0020 - 0021
002E - 002F
0040 - 0043
0048 - 004B
004E - 004F
0060 - 0060
0061 - 0061
0064 - 0064
0070 - 0073
0080 - 008F
0092 - 0092
00A0 - 00A1
00C0 - 00DF
00F0 - 00FF
0100 - 017F
0180 - 01BF
01C0 - 01CF
01F0 – 01FF
0200 - 027F
0279 - 0279
0295 - 0296
02F8 - 02FF
0300 - 033F
0340 - 035F
0378 - 037F
03B0 - 03BA
03C0 - 03DF
03F0 - 03F7
03F8 - 03FF
0480 - 048F
04D0 - 04D1
0A79 - 0A79
1200 - 1207
1220 - 1227
DF80 - DFFF
EFF0 - EFFF
TME-104-CLR-LX800-R1V3.doc
DMA-Controller
Programmable Interrupt controller
System
System timer
System timer
Super I/O
Keyboard
System speaker
Keyboard
System CMOS/Real-time clock
DMA-Controller
System
Programmable Interrupt controller
DDMA-Controller
Numeric Coprocessor
PCI-ISA Bridge Positive Decode Range 1
PCI-ISA Bridge Positive Decode Range 2
PCI-ISA Bridge Positive Decode Range 3
IDE Controller
PCI-ISA Bridge Positive Decode Range 4
ISA-PnP-Data port
LPC-Bus
COM2
PCI-ISA Bridge Positive Decode Range 5
PCI-ISA Bridge Positive Decode Range 6
LPT1
Advanced Micro Devices Win XP Graphics Driver
Advanced Micro Devices Win XP Graphics Driver
Standard-Floppy controller
COM1
DMA-Controller
Programmable Interrupt controller
ISAPnP-Data port
SPI-Flash
Simple-I/O (default)
Not used
Standard-Dual-Channel-PCI-IDE-Controller
Rev. 1.3
Description
51(53)
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