Varian Data 620/i System Reference Manual page 90

n
n+1
n
n+l
MULl
Multiply Immediate
Timing: 10 cycles (16 bits)
(optional) 11 cycles (18 bits)
17 16
15 14 13 12 11
10
9 8
7 6 5 4 3 2 1 0
r-r-
I
I
I I
00 6
160
1--4--
I
I
Operand
til
18-bi!.
option
The contents of the
B
register are multiplied
by
the contents of
the operand at location n
+
1. The ori ginal contents of the
A register are added to the final product. The product is placed
in the A and B registers, with the most-significant half of the
product in the A register and the least-significant half in the
B
register. The sign of the product is contained in the sign
position of the A register. The sign position of the B register
is reset to zero.
The algorithm is in the form
R • B +
A.
Indexing: No
Indirect Addressing: No
Registers Altered:
A, B,
OF
Divide Immediate Timing: 10-14 cycles (16 bits)
(optional) 11-15 cycles (18 bits)
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
r-r
~_+_4-
___
0_0 ____
~1_6
__
~1
______
1_70 ______
~
I I
~_.L_
L!.
8
-i:!.!.
option
Operand
The contents of the A and
B
registers are divided by the contents
of the operand at location n + 1. The quotient is placed in the
B register with sign, and the remainder is placed in the A
register with the sign of the dividend.
If
(A, B)
~
:s1
3-63