Varian Data 620/i System Reference Manual page 23

n
n+1
2-10
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
a
r -
T" -
-r-------~----_.__--------
__
I
l e o
D
L_..L. _
...1.-_ _ _ _ _ - - - ' _ _ _ _ """"-_ _ _ _ _ _ _ _ _ - '
LC'ass cadeJlo
p
cadelL
Definitian~
17 16 15 14 13 12 11 10
9 8
7 6 5 4
3
2 1
a
'-1-,
I
Address
L_~
_
~.__:_--L.-------_------------'
~8-brJ
option
__________ {I
= 0, word contains an address
I
=
1, word contains an indirect address
Figure
2-6.
Double-Word Addressing Instruction Format
For the extended address group of instructions, the definition
field is further divided into three subfields. The M field
contains bits
0-2,
the op code contains bits
3-6,
with bits
7 and 8 left blank. Extended address instructions are
identical in operation to the single-word addressing instruc-
tions except that they allow direct addressing to
32,768
words of memory.
For the memory input/output group, the definition field of
the first word contains the number of the peripheral device
and its mode, and the second word contains the memory
address of the data to be transferred. Indirect addressing
is not permitted.
Non-addressing instructions. The double-word non-addressing
instruction format is shown in figure
2-7.
This format is
used for the immediate group of instructions. There are
12
standard and two optional instructions in this group.
The op:.code field contains the operation to be performed
(bits
3-6).
All sing Ie-word addressing type instructions may
be performed as ani mmedia te type j nstru ctj on. The operand
is contained in the second word. Indirect addressing is not
applicable.