3-24
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
00
5
I
step
I
X
B A
I
X
B A
I
----~~
L....-_--I
l
Desti~ation
Register
Source Reg i ster
00 Transfer
01 Increment
10 Complement
11 Decrement
10
Execute Unconditional
11
Execute Condition on Overflow Set
Figure 3-7. Register Change Instruction
~
Increment A Register
Timing:
17 16 15 14 13 12 11
10 9 8 7 6 5
4
3 2
,-T-!
00
5
111
L._~_
118-bit
I
option
~
Increment B Register
Timing:
17 16 15 14 13 12 11
10 987 6 5
4 3
2
1-'-
!
L_~_
00
5
122
118-bit
I
option
1 cycle
1 0
1 cycle
1 0
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