Varian Data 620/i System Reference Manual page 41

3-14
ANA AND Memory and A
Timing: 2 cycles
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
0
~-T-!
15
M A
L_..J.. _ .......
----_---I~
___ ........ ________
_ _ _ I
I
la-bit
I
option
The logical-AND is performed between the contents of the A
register and the contents of the effective memory location.
The result is placed in the A register. If the same bit position
of both the effective memory location and A contain a one,
the result is a one. The truth table is shown below, where
n
=
bit position:
Condition
Effective
Memory
A(n}
Location (n)
0
a
0
1
1
a
1 1
Indexing: Yes
Indirect Addressing: Yes
Registers Altered: A
3.2.2 Single-Word Non-Addressing Instructions
Result
A(n}
0
0
0
1
The format of the single word non-addressing instruction class
is shown in figure 2-5.
The non-addressing single-word instructions include the control
group, the shift group, and the register change group. The
operation is defined by the M field. The address field (A) is
not used by the control group instructions. For the shift group,
the A fi e Id defi nes the type and number of sh ifts. For the
register change group, the A field defines the type of transfer
and the registers affected.