Varian Data 620/i System Reference Manual page 17

2-4
A register. This full-length register is the upper half of the
accumulator. This register accumulates the results of logical
and addition/subtraction operations, the most-significant
half of the double-length product in multiplication, and the
remainder in division.
It
may also be used for input/output
transfers under program control.
B register. This full-length register is the lower half of the
accumulator. This register accumulates the least-significant
half of the double-length product in multiplication, and the
quotient in division.
It
may also be used for input/output
transfers under program control and as a second hardware
index reg i ster .
X register. This full-length register permits indexing of
operand addresses without adding time to execution of
indexed instructions.
P register. This full-length register holds the address of the
current instruction and is incremented before each new
instruction is fetched. A full complement of instructions is
available for conditional and unconditional modification of
this register.
S register. This five-bit register controls the length of shift
instructions in combination with the U register.
2. 1.4 I nterna I Buses
The basi c computer contains five buses. These are the
(, S, W, L, and
I/O
buses. Buses (, S, W, and Lore
described in the following paragraphs. The
I/O
bus is
descri bed in paragraph 2. 1 .5.
(bus. This bus provides the parallel path and selection logic
for routing data between the arithmetic unit, the
I/O
bus,
the operational registers, and the memory registers. The
console display indicators are also driven from the ( bus.
Distribution of data simultaneously to multiple operational
registers is facilitated by this bus.
S bus. Th is bus provides the parallel path and selection log ic
for routing data from the operational registers to the
ari thmeti c uni t.