Varian Data 620/i System Reference Manual page 9

1-4
Specifi cati on
Instruction Types
Instructions
Micro-EXEC
(optional)
Table 1-1. (Continued)
P
Register
U
Register
L Register
W Register
S Register
R Register
Control
Characteristi cs
Instruction counter, 16 or 18 bits.
Instruction register, 16 bits.
Memory address register, 16 bits.
Memory word register, 16 or 18
bits.
Shift register,
5
bits.
Operand register, 16 or 18 bits.
Addressing Modes Six as follows:
Direct: to 2048 words.
Relative to P register: to 512 words.
Index with X register hardware: to 32,768 words (does not
add to execution time).
Index with B register hardware: to 32,768 words (does not
add to execution ti me).
Multilevel indirect: to 32,768 words.
Immediate: operand immediately follows instruction.
Extended: operand address immediately follows instruc-
tion
(optional): to 32,768 words.
Four, as follows:
Single word, addressing.
Single word, non-addressing.
Doub
I
e word, addressi ng •
Doub
I
e word, non-add ressi ng .
107 standard, approximately 200 microinstructions, plus
18 optional.
Faci
I
ity and hardware to construct a hardwired program
external to the DATA 620/i. Eliminates stored program
memory accessing for hardwi red programs.