Zynq Configuration - Digilent Arty Z7 Reference Manual

26 RXD3
27 RXCTL
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48 (N/C)
49 (N/C)
50 (N/C)
51 (N/C)
52 MDC
53 MDIO
Table 2.1. MIO Pinout

3 Zynq Configuration

Unlike Xilinx FPGA devices, APSoC devices such as the Zynq-7020 are designed around the
processor, which acts as a master to the programmable logic fabric and all other on-chip
peripherals in the processing system. This causes the Zynq boot process to be more similar to
that of a microcontroller than an FPGA. This process involves the processor loading and
executing a Zynq Boot Image, which includes a First Stage Bootloader (FSBL), a bitstream
for configuring the programmable logic (optional), and a user application. The boot process is
broken into three stages:
Arty Z7 Reference Manual
DATA4
DIR
STP
NXT
DATA0
DATA1
DATA2
DATA3
CLK
DATA5
DATA6
DATA7
CCLK
CMD
D0
D1
D2
D3
RESETN
CD
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