Silicon Laboratories C8051F2 Series User Manual page 7

6.4. Analog I/O (J5, J6, J7, Terminal Block)
An Analog I/O Configuration connector (J6) provides the ability to route analog I/O signals from the C8051F2xx to
a terminal block in addition to connector J2 by installing shorting blocks on J6. Additionally, if shorting blocks are
installed on J5 and J7, the analog signals routed through J6 can be inputs to the C8051F2xx at port pins P3.0
and/or P3.1. The port pins can then be configured as inputs to the on-chip ADC for evaluation. J6 also allows the
user to route analog signals from the terminal block to port pins P1.3 and P1.4. These port pin can then be
configured as inputs to Comparator 1. The PWM signal from the low-pass filter is also routed to J6 to provide a
user controlled analog voltage level. This signal can then be used to evaluate the on-chip ADC by placing a
shorting block on J6 (provided the J5 or J7 header is shorted). Refer to Figure 3 to determine the shorting block
installation positions required to create the desired analog signal paths. Refer to Table 3 for terminal block
connections and Table 4 for J6 pin definitions.
6.5. VDD Monitor Disable (J1)
The VDD Monitor of the C8051F2xx may be disabled by moving the shorting block on J1 from pins 1-2 to pins 2-3,
as shown in Figure 4.
P1.4/CP1-
AIN1
AIN2
GND P1.3/CP1+
Vref
Figure 3. J6 Analog I/O Configuration Connector
Table 3. Terminal Block Pin Descriptions
Pin #
1
2
7
8
Table 4. J6 Connector Pin Descriptions
Pin #
1
2, 9, 10
3
4
5
6
7
8
MONEN
Figure 4. VDD Monitor Hardware Setup
Pin 1
Pin 2
J5
AIN2 P3.0AIN
PWM
AIN1 P3.1AIN
J7
J6
Description
VREF
GND
AIN2
AIN1
Description
P1.4/CP1-
NC
AIN2
P3.0AIN
P1.3/CP1+
PWM
AIN1
P3.1AIN
1
2
3
Rev. 0.6
C8051F2xx-DK
P3.0
P3.1
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