Table of Contents
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68000 Motherboard User's Manual
TABLE OF CONTENTS
1
INTRODUCTION .......................................................... 4
2
DESIGN MOTI VATION .................................................. 4
3
DESIGN INSPI RAT ION ................................................. 4
4
WHAT I S A COMPUT ER? ............................................... 7
5
THE M B68K-100 COMPUT ER ....................................... 13
5.1
MB 68k -10 0 Spe ci fi cat ion ........................................................13
5.2
Wh at' s What an d Wh ere I s I t ..................................................15
6
ARCHIT ECT URAL OVERVIEW ........................................ 15
6.1
Basic Bl ock Lev el De scrip tio n .................................................16
6.2
Gli mp se of th e 68 000 ..............................................................18
6.3
Bus Ar ch ite ct ure of the 680 00 ................................................18
6.4
Bus Con tro l Sig nal Ti ming .......................................................19
6.4.1
Regul ar Bu s Cy cle Ter minat ion .............................................19
6.4.2
Bus Te r min atio n i nto a 6 800 Bu s C ycle .................................22
7
CIRCUIT DESCRIPT ION ............................................... 22
7.1
Po wer Inp ut ...........................................................................22
7.1.1
Volta ge Regu lat ion ..............................................................23
7.1.2
Act ive Rev er sed Conn e ctio n P rote ction ...............................23
7.1.3
Discr ete Vo ltag e Supe rvi so r ................................................23
7.2
The 6 8000 Mi cr opro ce sso r ......................................................24
7.3
The 'Pin ter ce pt' Hea der s ........................................................24
7.4
Indi ca tor s ..............................................................................24
7.5
The Sy st e m C lo ck ....................................................................25
7.6
Ext erna l R un C ont rol ..............................................................27
7.7
Reset P ul se Gene rat or ............................................................27
7.8
The St art Ve cto r Sel ector (SVS) ...............................................28
7.9
Addre ss Sp ace Ma ppin g ..........................................................29
7.10
Data Strob ed Fl o w Log i c .......................................................30
7.11
Bus Cy cl e Te r mi nati on ..........................................................30
7.11. 1
Bus Te r min atio n with Aut o /DTA CK .....................................31
7.11. 2
Bus Te r min atio n with /VPA .................................................31
7.11. 3
Bus Te r min atio n with /BERR ...............................................31
7.11. 4
Wa it State Gen era tor .........................................................32
7.12
On-Boar d Pe rip hera l s ...........................................................32
7.12. 1
Inter rup t Enab le Reg ister ..................................................33
7.12. 2
The C lo ck Sy n chro niza tio n Re gi ste r ...................................33
7.12.2.1
On-Board Interrupt Logic Level ..................................................... 34
7.12.2.2
The Hardware Entropy Generator .................................................. 34
7.12.2.3
On-Board Digital Input Interface .................................................. 36
Page 2 of 54
Rev. A
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