Motorola MB68k-100 User Manual page 20

68000 Motherboard User's Manual Rev. A
clock edge between them, then no sequencing order is required. Put simply, data on the
data bus must be established for the first falling clock edge once /DTACK is asserted.
Write cycles require that the data on the bus be maintained by the processor for long
enough to meet the hold time write requirement of the target device. As with the Read
cycle, the processor examines /DTACK on the falling edge of the clock to close the Write
cycle. /DTACK control logic must therefore provide sufficient delay for the memory
device's write operation to complete after the bus control signals from the processor are
issued. Unlike the one and a half clock periods available in the Read cycle before the
/DTACK signal is first checked, the Write cycle provides only one half of a clock cycle
before first examination of /DTACK to end the bus cycle. However, the write data and
control signals remain present for one clock cycle after termination of the bus cycle,
providing a total of one and a half clock periods for the memory device to complete its
internal write operation. The total time available for the target device, therefore, is again
one and a half clock periods.
Since memory devices tend to be slow, care must be taken that the /DTACK signal does
not prematurely close the bus cycle. On a Read cycle, the processor first checks
/DTACK's state one and a half clock cycles after the processor has set up the control
signals. This allows that much time for the addressed device to present its valid data onto
the bus, before special timing control is needed for /DTACK. On a Write cycle, only one
half of a clock cycle elapses before /DTACK is tested to close the cycle. However,
because the write data and control signals remain valid for a clock cycle after termination
of the bus cycle, the time available to the bus device without special /DTACK timing
provisions is also one and a half clock cycle periods.
Because the 68000 bus architecture uses the /DTACK termination signal to close the bus
cycle, the speed of the devices on the bus places no constraint on the maximum processor
clock frequency. However, the bus throughput is optimized with a bus design that
minimizes the need for processor wait states. Wait states are inserted by the processor
while interfacing with the memory device when the /DTACK signal is not asserted upon
the falling edge of the processor clock. To incur no wait states, Read and Write cycles
must complete within one and a half clock cycles. This period starts from the set up of
all bus control signals and ends upon assertion of the /DTACK signal.
Delving deeper into bus cycle timing details, the processor state over the bus cycle
changes on each phase of the clock signal. In a Read cycle, as seen in Figure 8 below,
the address lines (A1-A23) are established at the falling edge starting state S1. The
remaining control signals (/AS, /UDS, /LDS & R/W ! ) are established at the rising edge
starting processor state S2. External bus circuitry may now complete the cycle. The
cycle termination signals are next checked by the processor at the falling edge at the end
of state S4. This provides a window of one and a half clock periods to complete the cycle
without requiring wait states. In a Write cycle, shown in Figure 9 below, A1-A23 are set
up at the start of S1, /AS and R/W ! are set up in S2, and then /UDS and /LDS are set up
on the rising edge starting state S4. As with the Read cycle, termination is next checked
at the falling edge closing state S4. This provides a window of only half of a clock
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