Support Logic; Reset Logic - Motorola M5271EVB User Manual

Table 1-3. D[20:19] External Boot Chip Select Configuration
1.3

Support Logic

1.3.1

Reset Logic

Reset occurs during power-on or via assertion of the signal RESET which causes the
MCF5271 to reset. RESET is triggered by the reset switch (SW3) which resets the entire
processor/system.
The dBUG Firmware configures the MCF5271 microprocessor internal resources during
initialization. The contents of the exception table are copied to address 0x0000_0000 in the
SDRAM. The Software Watchdog Timer is disabled, the Bus Monitor is enabled, and the
internal timers are placed in a stop condition. A memory map for the entire board can be
seen in Table 1-2.
If the external RCON pin is asserted (SW4-1 ON) during reset, then various chip functions,
including the reset configuration pin functions after reset, are configured according to the
levels driven onto the external data pins. See tables below on settings for reset
configurations.
If the RCON pin is not asserted (SW4-1 OFF) during reset, the chip configuration and the
reset configuration pin functions after reset are determined by the RCON register or fixed
defaults, regardless of the states of the external data pins.
SW4-1 Reset Configuration
OFF RCON not asserted, Default Chip configuration or RCON register settings
ON RCON is asserted, Chip functions, including the reset configuration after reset,
are configured according to the levels driven onto the external data pins.
SW4-2 JTAG Enable
OFF JTAG interface enabled
ON BDM interface enabled
D[20:19] Boot Device/Data Port Size
00 External (32-bit)
01 External (16-bit)
10 External (8-bit)
11 External (32-bit)
Table 1-4. SW4-1 RCON
Table 1-5. SW4-2 JTAG_EN
Chapter 1. M5271EVB Introduction
Support Logic
1-9