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68000 Motherboard User's Manual
Rev. A
Figure 11: Clock Frequency Divider Overview
7.6 Exter nal Run Contr ol
Inputs are provided within the stack connector interface to command the system's /HALT
and /RESET signals. These are the HALT_CMD and RESET_CMD inputs, appearing at
A1CON160/162, pins 22 and 24 respectively. When left open, these inputs do not
interfere with the operation of these signals. However, asserting the inputs as logic high
commands the corresponding control signal to be asserted. These inputs provide a means
of externally controlling the Halt and Reset signal states of the system.
Following power-up, the 68000 processor must be held in reset with both /HALT and
/RESET lines asserted for a minimum of 100ms. This functionality may be provided by
the on-board Discrete Voltage Supervisor. For a subsequent reset after power-up, a pulse
of a minimum of 10 clock cycles must be applied to both /HALT and /RESET together to
accomplish the processor reset. For further detail, see reference number 56 in the 'AC
Electrical Specifications' section of the Motorola 68000 User's Manual.
7.7 Res et Puls e Gener at or
The Reset Pulse Generator's function is simple. It generates a pulse of at least one clock
cycle when the processor reset signal, /RESET, is released. It provides both positive and
negative polarity pulses on RST_PULSE and /RST_PULSE lines respectively, which are
made available on positions 25 and 26 of A1CON160/162. Only the /RST_PULSE
signal is used by the MB68k-100 circuitry. Internally, this reset pulse is used to latch on-
board peripheral write registers to their initial, start-up values. These registers catch the
value of the LSB data bus, which has pull-down resistors that dominate during reset. The
on-board registers, therefore, start with a zero value.
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