Akai PDP42Z5TA Service Manual page 85

CREGB, ADC Input Enable (
ADDR[3:0]
BIT 7
Hex 0B X
Default Value 1
AMUX[4:0]: ADC Input Channel Enable.
00001: - AIN1
00010: - AIN2
00100: - AIN3
01000: - AIN4
10000: - AIN5
CREGC, ADC Input Gain Selection (
ADDR[3:0]
BIT 7
Hex 0C
1
Default Value
LGAIN[3:0] is for ADC Left Channel Gain Select While RGAIN[3:0] is for Right Channel Gain Select
1111 corresponds to +6 dB and 0000 to -9 dB with -1dB step
CREGD, Chip Soft Reset (
ADDR[3:0]
BIT 7
Hex 0D
Default Value 1
Chip Soft Reset; A write of all zeros to this register will reset the chip except the Command Registers.
Another write of hex92 is required to enable to chip again.
=hex0B, default=hex01)
ADRS
BIT 6 BIT 5 BIT 4
X X
0 0 0
=hex0C, default=hex99)
ADRS
BIT 6 BIT 5 BIT 4
LGAIN[3:0]
0 0 1
=hex0D, default=hex92)
ADRS
BIT 6 BIT 5 BIT 4
0 0 1
83／148
CREG1[7:0]
BIT 3 BIT 2
AMUX[4:0]
0 0
CREG1[7:0]
BIT 3 BIT 2
RGAIN[3:0]
1 0
CREG1[7:0]
BIT 3 BIT 2
RESET[7:0]
0 0
CE2836
BIT 1 BIT 0
0 1
BIT 1 BIT 0
0 1
BIT 1 BIT 0
1 0