Akai PDP42Z5TA Service Manual page 84

CREGA, Chip Control Register (
ADDR[3:0]
BIT 7
Hex 0A
DAMSTR
Default Value 0
DAMSTR: Configure the DAC PCM Serial Port.
0: - Slave Mode
1: - Master Mode.
DAPWD:
DAC Power Down
0: DAC enabled
1: DAC Power Down.
ADMSTR: Configure the ADC PCM Serial Port.
0: - Slave Mode
1: - Master Mode.
ADPWD:
ADC Power Down
0: ADC enabled
1: ADC Power Down.
ZCBYP:
Disable ADC Zero Crossing Detection
0: Zero crossing is enabled.
1: Zero crossing is bypassed.
HPFBYP: Bypass ADC data path High Pass Filter
0: Enable high pass filter.
1: Disable high pass filter.
=hex0A, default=hex00)
ADRS
BIT 6 BIT 5 BIT 4
DAPWD X X
0 0 0
82／148
CREG1[7:0]
BIT 3 BIT 2
ADMSTR ADPWD
0 0
CE2836
BIT 1 BIT 0
ZCBYP HPFBYP
0 0