Akai PDP42Z5TA Service Manual page 69

Description (continue)
The DAC support conversion rate from 32K to 192KHz while the ADC from 32K to 96K. The CE2836 support 32, 24, 20 and
16-bit input data. It also support multiple sampling frequency data. Each DAC has its own individual volume control.
XCK REQUIREMENT
The CE2836 supports 32K, 44.1K, 48K, 96K and 192K sampled audio in DAC operations and32K, 44.1K, 48K and 96K
sampled audio in ADC operations. The oversampled clock, XCK, requirements are listed in Table 1 and 2.
The DAC and ADC PCM serial port can be configured as 'Master' or 'Slave' independently and each has separated over
sampling clock input. In the 'Slave Mode' PCM serial port operation if the AUTODEC, CR1[7]==1,there is an clock
frequency detection circuit to set up the system clock, the users don't need to set the SRC registers. However in the 'master
mode' operation the users need to set the SCR registers for the serial audio clock generations
Sampling
Rate
XCK Freq
32 K
SRC[1:0]
XCK Freq
44.1K
SRC[1:0]
XCK Freq
48 K
SRC[1:0]
XCK Freq
96 K
SRC[1:0]
XCK Freq
192 K
All the XCK clock rate listed are supported in the 'Slave Mode'
SRC Registers are used in the 'Master Mode'. (#) are not supported in the in the 'Master Mode' .
DAC AUTODET is CREG1[7], DAC SRC[1:0]are CREG1[6:5] and DACDIV is CREG1[4].
Table 1.
DAC XCK Requiremen
DACDIV==0
12.288 MHz
[11], 384 fs
16.934 Mhz
[11], 384fs
18.432 MHz
[11], 384 fs
18.432 MHz
[01], 192 fs
18.432 Mhz
SRC (#), 96 fs
t
8.192 Mhz. 24.576 Mhz
(#), 256 fs [11], 768fs
11.29 Mhz. 33.869 Mhz
[10], 256 fs [11], 768 fs
12.288 Mhz 36.864 MHz
[10], 256 fs [11], 768fs
12.288 Mhz. 36.864 MHz
[00], 128 fs [01], 384 fs
12.288 Mhz. 36.864 MHz
(#), 64 fs (#), 192 fs
67／148
CE2836
DACDIV==1
16.384 Mhz
(#), 512 fs
22.579 Mhz
[10], 512fs
24.576 Mhz.
[10], 512 fs
24.576 Mhz.
[00], 256 fs
24.576 Mhz.
(#), 128 fs