Akai PDP42Z5TA Service Manual page 80

CREG1, DAC Control Register 1(
ADDR[3:0]
BIT 7
Hex 01
AUTODET
Default Value 1
AUTODET
Automatically detects the serial audio input data sampling rate clock frequency.
0: - do not use auto-detect
1: - automatically detects the serial audio input data sampling rate and clock frequency.
SRC[1:0]: - DAC Sampling Rate Selection. It is used in the DAC Master Mode, CRA[7]==1, to generate DAFS and
DABCK.
00: - Sampling Rate = XCK/128.
01: - Sampling Rate = XCK/192.
10: - Sampling Rate = XCK/256.
11: - Sampling Rate = XCK/384.
CKDIV2: - Enable the ADXCK Clock divided by 2.
0: - DAC system clock is DAXCK (default)
1: - DAC system clock is DAXCK/2
MUTE56:
Mute control for channels 5 and 6
0: do not mute channels 5 and 6
1: simultaneously mute channels 5 and 6
MUTE34:
Mute control for channels 3 and 4
0: do not mute channels 3 and 4
1: simultaneously mute channels 3 and 4
MUTE12:
Mute control for channels 1 and 2
0: do not mute channels 1 and 2
1: simultaneously mute channels1 and2
=hex01, default=hex80)
ADRS
BIT 6 BIT 5 BIT 4
SRC[1:0] CKDIV2
0 0 0
78／148
CREG1[7:0]
BIT 3 BIT 2
X MUTE56
0 0
CE2836
BIT 1 BIT 0
MUTE34 MUTE12
0 0