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Product Specification of 42XGA PDP Module
LVDS Signal (continued)
Signal Input sequence of LVDS Receiver
RxCLK IN
(Differential)
Previous cycle
RE
R1-1
RD
R3-1
B7-1
RC
G6-1
RB
R5-1
RA
8bit application
TA+/-
TB+/-
TC+/-
TD+/-
3.3V
Video Board Side
※ To use (only) 8bit video signal, "TE+" is to be tied to ground signal and
"TE-" is to be tied to 3.3V signal. (to set the 2 LSB of 10 bits video signal to '0')
10bit application
TA+/-
TB+/-
TC+/-
TD+/-
TE+/-
Video Board Side
☞ Default 8 bit input ( For 10 bit input, it need to discuss with PDP Division )
R0-1
NC
B1
R2-1
NC
B3
B6-1
DE
VS
G5-1
B5
B4
R4-1
G4
R9
twisted
pair cable
TE-
TE+
GND
(VSC)
twisted
pair cable
(VSC)
111／148
Next cycle
B0
G1
G0
R1
B2
G3
G2
R3
HS
B9
B8
B7
G9
G8
G7
G6
R8
R7
R6
R5
※ DE : BLANK, VS : Vsync, HS : Hsync
RA+/-
RB+/-
RC+/-
RD+/-
RE+/-
PDP module side
RA+/-
RB+/-
RC+/-
RD+/-
RE+/-
PDP module side
R0
R2
B6
G5
R4
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