Ip429Ii_Status0; Figure 6 Ip-429 Status Register 0 Bit Map - Dynamic Engineering IP-429-II User Manual

IP429II_STATUS0

[$0A 429 Control Register Port read only
DATA BIT
FIGURE 6
The DRx bits are the Data Ready status outputs from the encoder/decoder devices.
The signals are buffered and inverted to create active high data ready signals. DR1 is
receiver 1 of device N. DR2 is receiver 2 of device N. Each of the 4 channels has 2
receivers. There are four devices and your hardware may not have all four installed.
Uninstalled devices should be masked off when reading this status register. These bits
can be used for polled operation of the receivers. The signals return to zero when the
data is read. The _oe1 addresses should be accessed for the receiver 1 data and the
_oe2 addresses for the receiver 2 data within each channel.
CONTROL REGISTER 1
7
6
5
4
3
2
1
0
Embedded Solutions
DESCRIPTION
DR2 device 4 1 = data ready, 0 = no data
DR1 device 4
DR2 device 3
DR1 device 3
DR2 device 2
DR1 device 2
DR2 device 1
DR1 device 1
IP-429 STATUS REGISTER 0 BIT MAP
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