Lab.gruppen PLM 20K44 Operation Manual page 86

10. Application Guide
10.6. Digital Clock Configuration
10.6.1. Digital Clock Overview
clocking system. The digital clock can generate various independent internal sample rates, or can sync to an
incoming AES3 signal. Figure 10.7 shows the various sample rates and options available.
INPUTS
AES1
AES2
C
DANTE
AES1
AES2
C
Table 10.7: Digital Clocking System
In Figure 10.7, each circled C represents a choice point. A choice point is a user-interface control that can be
information.
NOTE: Figure 10.7 indicates internally generated clocks with base-rate multiples of 44.1 kHz or 48 kHz.
This should not be confused with the internal DSP sample rate of 96 kHz.
The PLM+ digital clocking system can either generate its own internal clock, or synchronize to an incoming
external clock source via the AES3 digital input.
10.6.2. Clock Source Priorities
compatible clock signal is preset.
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PLM+ SERIES Operation Manual rev 3.0.1
INTERNAL
48 kHz
48 kHz
PRIMARY
96 kHz
CLOCK
192 kHz
INTERNAL
48 kHz
AUTO /
48 kHz
MANUAL 48
C
96 kHz
SAMPLE RATE
192 kHz
CONVERTER
44.1 kHz
CLOCK
88.2 kHz
C
AUTO /
176.4 kHz
MANUAL 44
INTERNAL
44.1 kHz
OUTPUTS
C Pwr 1
Pwr 2
C
C Pwr 3
C Pwr 4
C Dante
Channel 1-8
48 / 96 kHz