Page 1 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. SH7125 , SH7124 Group Group Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family SH7125 R5F7125 SH7124 R5F7124 Rev.3.00 Revision Date: Sep. 27, 2007...
Page 2 Rev. 3.00 Sep. 27, 2007 Page ii of xx...
Page 3 Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures.
Page 4: General Precautions On Handling Of Product
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Page 5 Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Page 6: Preface
Preface The SH7125 Group and SH7124 Group RISC (Reduced Instruction Set Computer) microcomputer include a Renesas Technology-original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using the SH7125 Group and SH7124 Group in the design of application systems.
Page 7 SH7125 Group and SH7124 Group manuals: Document Title Document No. SH7125 Group, SH7124 Group Hardware Manual This manual SH-1/SH-2/SH-DSP Software Manual REJ09B0171 User's manuals for development tools: Document Title Document No. SuperH RISC engine C/C++ Compiler, Assembler, REJ10B0152 Optimizing Linkage Editor Compiler Package V.9.00 User's Manual SuperH RISC engine High-performance Embedded Workshop 3 REJ10B0025...
Page 8 Rev. 3.00 Sep. 27, 2007 Page viii of xx...
Page 9: Table Of Contents
Contents Section 1 Overview....................1 Features of SH7125 and SH7124................... 1 Block Diagram........................6 Pin Assignments ........................7 Pin Functions ........................11 Section 2 CPU......................17 Features..........................17 Register Configuration......................18 2.2.1 General Registers (Rn).................... 19 2.2.2 Control Registers ....................19 2.2.3 System Registers.....................
Page 10 Address Map ........................51 Initial State in This LSI......................54 Note on Changing Operating Mode ..................54 Section 4 Clock Pulse Generator (CPG) .............55 Features..........................55 Input/Output Pins......................... 58 Clock Operating Mode......................59 Register Descriptions ......................61 4.4.1 Frequency Control Register (FRQCR) ..............61 4.4.2 Oscillation Stop Detection Control Register (OSCCR) ..........
Page 11 5.5.4 General Illegal Instructions..................82 Cases when Exceptions are Accepted .................. 83 Stack States after Exception Handling Ends................ 84 Usage Notes ......................... 86 5.8.1 Value of Stack Pointer (SP) ..................86 5.8.2 Value of Vector Base Register (VBR) ..............86 5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling..
Page 12 7.2.9 Break Data Mask Register B (BDMRB)............... 124 7.2.10 Break Bus Cycle Register B (BBRB) ..............125 7.2.11 Break Control Register (BRCR) ................127 7.2.12 Execution Times Break Register (BETR)............. 131 7.2.13 Branch Source Register (BRSR)................132 7.2.14 Branch Destination Register (BRDR)..............133 Operation ...........................
Page 13 9.3.13 Timer General Register (TGR) ................209 9.3.14 Timer Start Register (TSTR) ................210 9.3.15 Timer Synchronous Register (TSYR)..............212 9.3.16 Timer Counter Synchronous Start Register (TCSYSTR) ........214 9.3.17 Timer Read/Write Enable Register (TRWER) ............. 216 9.3.18 Timer Output Master Enable Register (TOER) ............ 217 9.3.19 Timer Output Control Register 1 (TOCR1) ............
Page 14 9.7.1 Module Standby Mode Setting ................332 9.7.2 Input Clock Restrictions ..................332 9.7.3 Caution on Period Setting ..................333 9.7.4 Contention between TCNT Write and Clear Operations........333 9.7.5 Contention between TCNT Write and Increment Operations....... 334 9.7.6 Contention between TGR Write and Compare Match .......... 335 9.7.7 Contention between Buffer Register Write and Compare Match ......
Page 15 10.3.6 Port Output Enable Control Register 2 (POECR2)..........394 10.4 Operation ........................... 396 10.4.1 Input Level Detection Operation ................396 10.4.2 Output-Level Compare Operation ................ 398 10.4.3 Release from High-Impedance State ..............398 10.5 Interrupts..........................399 10.6 Usage Note......................... 400 10.6.1 Pin State when a Power-On Reset is Issued from the Watchdog Timer ....
Page 16 12.4.4 Multiprocessor Communication Function ............463 12.4.5 Multiprocessor Serial Data Transmission ............. 465 12.4.6 Multiprocessor Serial Data Reception ..............466 12.5 SCI Interrupt Sources......................469 12.6 Serial Port Register (SCSPTR) and SCI Pins ..............470 12.7 Usage Notes ........................471 12.7.1 SCTDR Writing and TDRE Flag................
Page 17 Section 14 Compare Match Timer (CMT) ............501 14.1 Features..........................501 14.2 Register Descriptions ......................502 14.2.1 Compare Match Timer Start Register (CMSTR) ..........503 14.2.2 Compare Match Timer Control/Status Register (CMCSR) ........503 14.2.3 Compare Match Counter (CMCNT) ..............505 14.2.4 Compare Match Constant Register (CMCOR) .............
Page 18 16.2.3 Port B Port Registers H and L (PBPRH and PBPRL) .......... 561 16.3 Port E ..........................564 16.3.1 Register Descriptions.................... 566 16.3.2 Port E Data Register L (PEDRL)................566 16.3.3 Port E Port Register L (PEPRL) ................569 16.4 Port F ..........................571 16.4.1 Register Descriptions....................
Page 19 Section 18 RAM ....................657 18.1 Usage Notes ........................658 18.1.1 Module Standby Mode Setting ................658 18.1.2 Address Error......................658 18.1.3 Initial Values in RAM................... 658 Section 19 Power-Down Modes ................659 19.1 Features..........................659 19.1.1 Types of Power-Down Modes ................659 19.2 Input/Output Pins.......................
Page 20 21.3.1 Clock Timing ......................710 21.3.2 Control Signal Timing ..................712 21.3.3 Multi Function Timer Pulse Unit 2 (MTU2) Timing..........715 21.3.4 I/O Port Timing..................... 717 21.3.5 Watchdog Timer (WDT) Timing................718 21.3.6 Serial Communication Interface (SCI) Timing............. 719 21.3.7 Port Output Enable (POE) Timing................ 721 21.3.8 A/D Converter Timing..................
Page 21: Section 1 Overview
Features of SH7125 and SH7124 This LSI is a single-chip RISC (Reduced Instruction Set Computer) microcomputer that integrates a Renesas Technology original RISC CPU core with peripheral functions required for system configuration. The CPU in this LSI has a RISC-type instruction set. Most instructions can be executed in one state (one system clock cycle), which greatly improves instruction execution speed.
Page 22 Section 1 Overview Table 1.1 Features Items Specification • Central processing unit with an internal 32-bit RISC (Reduced Instruction Set Computer) architecture • Instruction length: 16-bit fixed length for improved code efficiency • Load-store architecture (basic operations are executed between registers) •...
Page 23 Section 1 Overview Items Specification • Interrupt controller External interrupt pins (INTC)  SH7125: Five pins (NMI and IRQ3 to IRQ0)  SH7124: Four pins (NMI and IRQ3 to IRQ1) • On-chip peripheral interrupts: Priority level set for each module •...
Page 24 Section 1 Overview Items Specification • Multi-function timer Maximum 16 lines of pulse input/output and three lines of pulse input pulse unit 2 (MTU2) based on six channels of 16-bit timers (SH7125) • Maximum 12 lines of pulse input/output and three lines of pulse input based on six channels of 16-bit timers (SH7124) •...
Page 25 Section 1 Overview Items Specification • 10 bits × 8 channels A/D converter (ADC) • Conversion request by external triggers or MTU2 • Two sample-and-hold function units (two channels can be sampled simultaneously) • I/O ports 37 general input/output pins and eight general input pins (SH7125) •...
Page 26: Block Diagram
Section 1 Overview Block Diagram The block diagram of this LSI is shown in figure 1.1. L bus (Iφ) Internal bus controller I bus (Bφ) Peripheral bus controller Peripheral bus (Pφ) H-UDI INTC Power- MTU2 port down (PFC) mode control [Legend] ROM: On-chip ROM...
Page 27: Pin Assignments
Section 1 Overview Pin Assignments 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PA3/IRQ1/RXD1/TRST PB3/IRQ1/POE1/TIC5V PA4/IRQ2/TXD1/TMS PB2/IRQ0/POE0 PA5/IRQ3/SCK1 PB1/TIC5W PA6/TCLKA PA7/TCLKB/SCK2/TCK PF7/AN7 PA8/TCLKC/RXD2/TDI PF6/AN6 PA9/TCLKD/TXD2/TDO/POE8 PF5/AN5 QFP-64 PA10/RXD0 PF4/AN4 LQFP-64 PF3/AN3 (Top view) PA11/TXD0/ADTRG PF2/AN2 PF1/AN1...
Page 28 Section 1 Overview 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PA3/IRQ1/RXD1/TRST PB3/IRQ1/POE1/TIC5V PA4/IRQ2/TXD1/TMS PB2/IRQ0/POE0 PA5/IRQ3/SCK1 PB1/TIC5W PA6/TCLKA PA7/TCLKB/SCK2/TCK PF7/AN7 PA8/TCLKC/RXD2/TDI PF6/AN6 PA9/TCLKD/TXD2/TDO/POE8 PF5/AN5 VQFN-64 PA10/RXD0 PF4/AN4 (Top view) PF3/AN3 PA11/TXD0/ADTRG PF2/AN2 PF1/AN1 PA12/SCK0 PF0/AN0...
Page 29 Section 1 Overview 36 35 34 33 32 31 30 29 28 27 26 PA1/POE1/TXD0 PB3/IRQ1/POE1/TIC5V PA3/IRQ1/RXD1/TRST PB1/TIC5W PA4/IRQ2/TXD1/TMS PA6/TCLKA PF7/AN7 PA7/TCLKB/SCK2/TCK PF6/AN6 LQFP-48 PF5/AN5 (Top view) PA8/TCLKC/RXD2/TDI PF4/AN4 PF3/AN3 PA9/TCLKD/TXD2/TDO/POE8 PF2/AN2 PF1/AN1 PE0/TIOC0A PF0/AN0 PE1/TIOC0B/RXD0 PE2/TIOC0C/TXD0 1 2 3 4 5 6 7 8 9 10 11 12 Pins for the system development tool.
Page 30: Manual
Section 1 Overview 39 38 37 36 35 34 33 32 31 30 29 28 27 PB3/IRQ1/POE1/TIC5V PA1/POE1/TXD0 PB1/TIC5W PA3/IRQ1/RXD1/TRST AVss PA4/IRQ2/TXD1/TMS PF7/AN7 PA6/TCLKA PF6/AN6 PA7/TCLKB/SCK2/TCK PF5/AN5 VQFN-52 PF4/AN4 (Top view) PF3/AN3 PA8/TCLKC/RXD2/TDI PF2/AN2 PF1/AN1 PA9/TCLKD/TXD2/TDO/POE8 PF0/AN0 PE0/TIOC0A AVcc PE1/TIOC0B/RXD0 PE2/TIOC0C/TXD0 1 2 3 4 5 6 7 8 9 10 11 12 13 Figure 1.3 (2)
Page 31: Pin Functions
Section 1 Overview Pin Functions Table 1.2 summarizes the pin functions. Table 1.2 Pin Functions Classification Symbol Name Function Power supply Power supply Power supply pin Connect all Vcc pins to the system. There will be no operation if any pins are open.
Page 32 Section 1 Overview Classification Symbol Name Function System control Power-on reset When low, this LSI enters the power- on reset state. MRES Manual reset When low, this LSI enters the manual reset state. WDTOVF Watchdog timer Output signal for the watchdog timer overflow overflow If this pin needs to be pulled down,...
Page 33 Section 1 Overview Classification Symbol Name Function Multi function timer- TIOC3A, MTU2 input The TGRA_3 to TGRD_3 input pulse unit 2 (MTU2) TIOC3B, capture/output capture input/output compare TIOC3C, compare output/PWM output pins TIOC3D (channel 3) TIOC4A, MTU2 input The TGRA_4 to TGRD_4 input TIOC4B, capture/output capture input/output compare...
Page 34 Section 1 Overview Classification Symbol Name Function A/D converter AVss Analog ground Ground pin for the A/D converter Connect it to the system ground (0 Connect all AVss pins to the system ground (0 V) correctly. The A/D converter does not work if any pin is open.
Page 35 Section 1 Overview Classification Symbol Name Function ASEMD0 E10A interface ASE mode Sets the ASE mode. When a low level is input, this LSI enters ASE mode. When a high level is input, this LSI enters the normal mode. The emulator functions are available in ASE mode.
Page 36 Section 1 Overview Rev. 3.00 Sep. 27, 2007 Page 16 of 758 REJ09B0243-0300...
Page 37: Section 2 Cpu
Section 2 Section 2 Features • General registers: 32-bit register × 16 • Basic instructions: 62 • Addressing modes: 11 Register direct (Rn) Register indirect (@Rn) Post-increment register indirect (@Rn+) Pre-decrement register indirect (@-Rn) Register indirect with displacement (@disp:4, Rn) Index register indirect (@R0, Rn) GBR indirect with displacement (@disp:8, GBR) Index GBR indirect (@R0, GBR)
Page 38: Register Configuration
Section 2 Register Configuration There are three types of registers: general registers (32-bit × 16), control registers (32-bit × 3), and system registers (32-bit × 4). General register (Rn) R15, SP (hardware stack pointer)* Status register (SR) 9 8 7 6 5 4 3 2 1 0 Q I3 I2 I1 I0 Global base register (GBR) Vector base register (VBR)
Page 39: General Registers (Rn)
Section 2 2.2.1 General Registers (Rn) There are sixteen 32-bit general registers (Rn), designated R0 to R15. The general registers are used for data processing and address calculation. R0 is also used as an index register. With a number of instructions, R0 is the only register that can be used. R15 is used as a hardware stack pointer (SP).
Page 40 Section 2 Read/ name Default Write Description Undefined S Bit Used by the multiply and accumulate instruction. Undefined T Bit Indicates true (1) or false (0) in the following instructions: MOVT, CMP/cond, TAS, TST, BT (BT/S), BF (BF/S), SETT, CLRT Indicates carry, borrow, overflow, or underflow in the following instructions: ADDV, ADDC, SUBV, SUBC, NEGC, DIV0U, DIV0S, DIV1, SHAR, SHAL, SHLR,...
Page 41: System Registers
Section 2 2.2.3 System Registers There are four 32-bit system registers, designated two multiply and accumulate registers (MACH and MACL), a procedure register (PR), and program counter (PC). • Multiply and accumulate registers (MACH and MACL) This register stores the results of multiplication and multiply-and-accumulate operation. •...
Page 42: Data Formats
Section 2 Data Formats 2.3.1 Register Data Format The size of register operands is always longwords (32 bits). When loading byte (8 bits) or word (16 bits) data in memory into a register, the data is sign-extended to longword and stored in the register.
Page 43: Immediate Data Formats
Section 2 2.3.3 Immediate Data Formats Immediate data of eight bits is placed in the instruction code. For the MOV, ADD, and CMP/EQ instructions, the immediate data is sign-extended to longword and then calculated. For the TST, AND, OR, and XOR instructions, the immediate data is zero- extended to longword and then calculated.
Page 44 Section 2 Load/Store Architecture: Basic operations are executed between registers. In operations involving memory, data is first loaded into a register (load/store architecture). However, bit manipulation instructions such as AND are executed directly in memory. Delayed Branching: Unconditional branch instructions means the delayed branch instructions. With a delayed branch instruction, the branch is made after execution of the instruction immediately following the delayed branch instruction.
Page 45 Section 2 Table 2.5 Access to Immediate Data Type This LSI's CPU Example of Other CPU 8-bit immediate #H'12,R0 MOV.B #H'12,R0 16-bit immediate MOV.W @(disp,PC),R0 MOV.W #H'1234,R0 ..DATA.W H'1234 32-bit immediate MOV.L @(disp,PC),R0 MOV.L #H'12345678,R0 ..DATA.L H'12345678 Note: * Immediate data is accessed by @(disp,PC).
Page 46: Addressing Modes
Section 2 Table 2.7 Access with Displacement Type CPU in this LSI Example of Other CPUs 16-bit displacement MOV.W @(disp,PC),R0 MOV.W @(H'1234,R1),R2 MOV.W @(R0,R1),R2 ..DATA.W H'1234 Note: * Immediate data is referenced by @(disp,PC). 2.4.2 Addressing Modes Table 2.8 lists addressing modes and effective address calculation methods. Table 2.8 Addressing Modes and Effective Addresses Addressing...
Page 47 Section 2 Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula Register @(disp:4, Effective address is register Rn contents with Byte: Rn + disp indirect with 4-bit displacement disp added. After disp is Word: Rn + disp × 2 displacement zero-extended, it is multiplied by 1 (byte), 2 Longword: Rn +...
Page 48 Section 2 Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC relative with @(disp:8, Effective address is PC with 8-bit displacement Word: PC + disp × 2 displacement disp added. After disp is zero-extended, it is multiplied by 2 (word) or 4 (longword), according Longword: to the operand size.
Page 49: Instruction Formats
Section 2 Addressing Instruction Calculation Mode Format Effective Address Calculation Method Formula PC relative Effective address is sum of PC and Rn. PC + Rn  Immediate #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. ...
Page 50 Section 2 Table 2.9 Instruction Formats Destination Operand Instruction Format Source Operand Sample Instruction   0 type xxxx xxxx xxxx xxxx  n type nnnn: register MOVT Rn direct xxxx nnnn xxxx xxxx Control register or nnnn: register STS MACH,Rn system register direct Control register or...
Page 51 Section 2 Destination Operand Instruction Format Source Operand Sample Instruction nm type mmmm: register nnnn: register Rm,Rn direct direct xxxx nnnn mmmm xxxx mmmm: register nnnn: register MOV.L Rm,@Rn direct indirect mmmm: post- MACH, MACL MAC.W @Rm+,@Rn+ increment register indirect (multiply- and-accumulate operation) nnnn: * post-...
Page 52 Section 2 Destination Operand Instruction Format Source Operand Sample Instruction d type dddddddd: GBR R0 (register direct) MOV.L @(disp,GBR),R0 indirect with displacement xxxx xxxx dddd dddd R0 (register direct) dddddddd: GBR MOV.L R0,@(disp,GBR) indirect with displacement R0 (register direct) MOVA @(disp,PC),R0 dddddddd: PC relative with displacement...
Page 53: Instruction Set
Section 2 Instruction Set 2.5.1 Instruction Set by Type Table 2.10 lists the instructions classified by type. Table 2.10 Instruction Types Kinds of Number of Type Instruction Op Code Function Instructions Data transfer Data transfer instructions Immediate data transfer Peripheral module data transfer Structure data transfer MOVA Effective address transfer...
Page 54 Section 2 Kinds of Number of Type Instruction Op Code Function Instructions Arithmetic MULS Signed multiplication operation MULU Unsigned multiplication instructions Sign inversion NEGC Sign inversion with borrow Binary subtraction SUBC Binary subtraction with carry SUBV Binary subtraction with underflow Logic Logical AND operation...
Page 55 Section 2 Kinds of Number of Type Instruction Op Code Function Instructions Branch Conditional branch, delayed conditional instructions branch (T = 0) Conditional branch, delayed conditional branch (T = 1) Unconditional branch BRAF Unconditional branch Branch to subroutine procedure BSRF Branch to subroutine procedure Unconditional branch Branch to subroutine procedure...
Page 56 Section 2 The instruction code, operation, and execution cycles of the instructions are listed in the following tables, classified by type. Summary of Execution Instruction Instruction Code Operation Cycles T Bit Indicated in MSB ↔ Indicated by mnemonic. Indicates summary of Value when no Value of T bit after LSB order.
Page 57: Data Transfer Instructions
Section 2 2.5.2 Data Transfer Instructions Table 2.11 Data Transfer Instructions Execution Instruction Operation Code Cycles T Bit  imm → Sign extension #imm,Rn 1110nnnniiiiiiii → Rn  (disp × 2 + PC) → Sign MOV.W @(disp,PC),Rn 1001nnnndddddddd extension → Rn ...
Page 58 Section 2 Execution Cycles Instruction Operation Code T Bit  Rm → (R0 + Rn) MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100  Rm → (R0 + Rn) MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101  Rm → (R0 + Rn) MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110  (R0 + Rm) → Sign MOV.B @(R0,Rm),Rn 0000nnnnmmmm1100 extension →...
Page 59: Arithmetic Operation Instructions
Section 2 2.5.3 Arithmetic Operation Instructions Table 2.12 Arithmetic Operation Instructions Execution Instruction Operation Code Cycles T Bit  Rn + Rm → Rn Rm,Rn 0011nnnnmmmm1100  Rn + imm → Rn #imm,Rn 0111nnnniiiiiiii Rn + Rm + T → Rn, ADDC Rm,Rn Carry...
Page 60 Section 2 Execution Cycles Instruction Operation Code T Bit  2 to 5* DMULU.L Rm,Rn Unsigned operation of 0011nnnnmmmm0101 Rn × Rm → MACH, MACL 32 × 32 → 64 bits Rn - 1 → Rn, if Rn = 0, 1 → Comparison 0100nnnn00010000 T, else 0 →...
Page 61: Logic Operation Instructions
Section 2 2.5.4 Logic Operation Instructions Table 2.13 Logic Operation Instructions Execution Instruction Operation Code Cycles T Bit  Rn & Rm → Rn Rm,Rn 0010nnnnmmmm1001  R0 & imm → R0 #imm,R0 11001001iiiiiiii  (R0 + GBR) & imm → AND.B #imm,@(R0,GBR) 11001101iiiiiiii (R0 + GBR)
Page 62: Shift Instructions
Section 2 2.5.5 Shift Instructions Table 2.14 Shift Instructions Execution Instruction Operation Code Cycles T Bit T ← Rn ← MSB ROTL 0100nnnn00000100 LSB → Rn → T ROTR 0100nnnn00000101 T ← Rn ← T ROTCL Rn 0100nnnn00100100 T → Rn → T ROTCR Rn 0100nnnn00100101 T ←...
Page 63: Branch Instructions
Section 2 2.5.6 Branch Instructions Table 2.15 Branch Instructions Execution Instruction Operation Code Cycles T Bit  If T = 0, disp × 2 + PC → 3/1* label 10001011dddddddd if T = 1, nop  2/1* BF/S label Delayed branch, if T = 0, 10001111dddddddd disp ×...
Page 64: System Control Instructions
Section 2 2.5.7 System Control Instructions Table 2.16 System Control Instructions Execution Instruction Operation Code Cycles T Bit 0 → T CLRT 0000000000001000 0 → MACH, MACL  CLRMAC 0000000000101000 Rm → SR Rm,SR 0100mmmm00001110 Rm → GBR  Rm,GBR 0100mmmm00011110 Rm →...
Page 65 Section 2 Execution Cycles Instruction Operation Code T Bit  MACH → Rn MACH,Rn 0000nnnn00001010  MACL → Rn MACL,Rn 0000nnnn00011010  PR → Rn PR,Rn 0000nnnn00101010  Rn–4 → Rn, MACH → (Rn) 0100nnnn00000010 STS.L MACH,@–Rn  Rn–4 → Rn, MACL → (Rn) 0100nnnn00010010 STS.L MACL,@–Rn ...
Page 66: Processing States
Section 2 Processing States The CPU has the five processing states: reset, exception handling, program execution, and power- down. Figure 2.4 shows the CPU state transition. From any state From any state when RES = 0 when RES = 1 and MRES = 0 RES = 0 Power-on reset state Manual reset state...
Page 67 Section 2 • Reset state The CPU is reset. When the RES pin is low, the CPU enters the power-on reset state. When the RES pin is high and MRES pin is low, the CPU enters the manual reset state. •...
Page 68 Section 2 Rev. 3.00 Sep. 27, 2007 Page 48 of 758 REJ09B0243-0300...
Page 69: Section 3 Mcu Operating Modes
Section 3 MCU Operating Modes Section 3 MCU Operating Modes Selection of Operating Modes This LSI has four MCU operating modes and three on-chip flash memory programming modes. The operating mode is determined by the setting of FWE, MD1, and MD0 pins. Table 3.1 shows the allowable combinations of these pin settings;...
Page 70: Input/Output Pins
Section 3 MCU Operating Modes Input/Output Pins Table 3.2 describes the configuration of operating mode related pin. Table 3.2 Pin Configuration Pin Name Input/Output Function Input Designates operating mode through the level applied to this pin Input Enables, by hardware, programming/erasing of the on-chip flash memory Operating Modes 3.3.1...
Page 71: Address Map
Section 3 MCU Operating Modes Address Map The address map for the operating modes are shown in figures 3.1 to 3.3. Mode 3 Single chip mode H'00000000 On-chip ROM (128 kbytes) H'0001FFFF H'00020000 Reserved area H'FFFF9FFF H'FFFFA000 On-chip RAM (8 kbytes) H'FFFFBFFF H'FFFFC000 On-chip peripheral...
Page 72 Section 3 MCU Operating Modes Mode 3 Single chip mode H'00000000 On-chip ROM (64 kbytes) H'0000FFFF H'00010000 Reserved area H'FFFF9FFF H'FFFFA000 On-chip RAM (8 kbytes) H'FFFFBFFF H'FFFFC000 On-chip peripheral I/O registers H'FFFFFFFF Figure 3.2 Address Map in SH7125, SH7124 (64 Kbytes Flash Memory Version) Rev.
Page 73 Section 3 MCU Operating Modes Mode 3 Single chip mode H'00000000 On-chip ROM (32 kbytes) H'00007FFF H'00008000 Reserved area H'FFFF9FFF H'FFFFA000 On-chip RAM (8 kbytes) H'FFFFBFFF H'FFFFC000 On-chip peripheral I/O registers H'FFFFFFFF Figure 3.3 Address Map in SH7124 (32 Kbytes Flash Memory Version) Rev.
Page 74: Initial State In This Lsi
Section 3 MCU Operating Modes Initial State in This LSI In the initial state of this LSI, some of on-chip modules are set in module standby state for saving power. When operating these modules, clear module standby state according to the procedure in section 19, Power-Down Modes.
Page 75: Section 4 Clock Pulse Generator (Cpg)
Section 4 Clock Pulse Generator (CPG) Section 4 Clock Pulse Generator (CPG) This LSI has a clock pulse generator (CPG) that generates an internal clock (Iφ), a bus clock (Bφ), a peripheral clock (Pφ), and a clock (MPφ) for the MTU2 module. The CPG also controls power- down modes.
Page 76 Section 4 Clock Pulse Generator (CPG) Figure 4.1 shows a block diagram of the CPG. Oscillator unit MTU2 clock (MPφ) Divider Crystal ×1/2 XTAL oscillator ×1/4 Internal clock PLL circuit ×1/8 (Iφ) (×8) EXTAL Peripheral clock Oscillation stop Oscillation (Pφ) detection circuit stop detection Bus clock...
Page 77 Section 4 Clock Pulse Generator (CPG) The clock pulse generator blocks function as follows: PLL Circuit: The PLL circuit multiples the clock frequency input from the crystal oscillator or the EXTAL pin by 8. The multiplication ratio is fixed at ×8. Crystal Oscillator: The crystal oscillator is an oscillator circuit when a crystal resonator is connected to the XTAL and EXTAL pins.
Page 78: Input/Output Pins
Section 4 Clock Pulse Generator (CPG) Table 4.1 shows the operating clock for each module. Table 4.1 Operating Clock for Each Module Operating Clock Operating Module Operating Clock Operating Module Internal clock (Iφ) Peripheral clock (Pφ)  Bus clock (Bφ) MTU2 clock (MPφ) MTU2 Input/Output Pins...
Page 79: Clock Operating Mode
Section 4 Clock Pulse Generator (CPG) Clock Operating Mode Table 4.3 shows the clock operating mode of this LSI. Table 4.3 Clock Operating Mode Source PLL Circuit Input to Divider ×8 EXTAL input or crystal resonator ON (×8) The frequency of the external clock input from the EXTAL pin is multiplied by 8 in the PLL circuit before being supplied to the on-chip modules in this LSI, which eliminates the need to generate a high-frequency clock outside the LSI.
Page 80 Section 4 Clock Pulse Generator (CPG) Table 4.4 Frequency Division Ratios Specifiable with FRQCR FRQCR Division Ratio Setting Clock Ratio Clock Frequency (MHz)* Multipli- cation Input Ratio Iφ Bφ Pφ MPφ Iφ Bφ Pφ MPφ Clock Iφ Bφ Pφ MPφ ×8 12.5 12.5...
Page 81: Register Descriptions
Section 4 Clock Pulse Generator (CPG) Register Descriptions The CPG has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 20, List of Registers Table 4.5 Register Configuration Abbrevia- tion...
Page 82 Section 4 Clock Pulse Generator (CPG) Initial Value Bit Name Description  Reserved This bit is always read as 0. The write value should always be 0. 14 to 12 IFC[2:0] Internal Clock (Iφ) Frequency Division Ratio Specify the division ratio of the internal clock (Iφ) frequency with respect to the output frequency of PLL circuit.
Page 83 Section 4 Clock Pulse Generator (CPG) Initial Value Bit Name Description 8 to 6 PFC[2:0] Peripheral Clock (Pφ) Frequency Division Ratio Specify the division ratio of the peripheral clock (Pφ) frequency with respect to the output frequency of PLL circuit. If a prohibited value is specified, subsequent operation is not guaranteed.
Page 84: Oscillation Stop Detection Control Register (Osccr)
Section 4 Clock Pulse Generator (CPG) 4.4.2 Oscillation Stop Detection Control Register (OSCCR) OSCCR is an 8-bit readable/writable register that has an oscillation stop detection flag and selects flag status output to an external pin. OSCCR can be accessed only in bytes. Bit: STOP Initial value:...
Page 85: Changing Frequency
Section 4 Clock Pulse Generator (CPG) Changing Frequency Selecting division ratios for the frequency divider can change the frequencies of the internal clock (Iφ), bus clock (Bφ), peripheral clock (Pφ), and MTU2 clock (MPφ). This is controlled by software through the frequency control register (FRQCR). The following describes how to specify the frequencies.
Page 86: Oscillator
Section 4 Clock Pulse Generator (CPG) Oscillator Clock pulses can be supplied from a connected crystal resonator or an external clock. 4.6.1 Connecting Crystal Resonator A crystal resonator can be connected as shown in figure 4.2. Use the damping resistance (Rd) listed in table 4.6.
Page 87: External Clock Input Method
Section 4 Clock Pulse Generator (CPG) Table 4.7 Crystal Resonator Characteristics Frequency (MHz) 12.5 Rs Max. (Ω) (Reference Values) Max. (pF) (Reference Values) 7 4.6.2 External Clock Input Method Figure 4.4 shows an example of an external clock input connection. In this case, make the external clock high level to stop it when in software standby mode.
Page 88: Function For Detecting Oscillator Stop
Section 4 Clock Pulse Generator (CPG) Function for Detecting Oscillator Stop This CPG detects a stop in the clock input if any system abnormality halts the clock supply. When no change has been detected in the EXTAL input for a certain period, the OSCSTOP bit in OSCCR is set to 1 and this state is retained until a power-on reset is input through the RES pin or software standby mode is canceled.
Page 89: Usage Notes
Section 4 Clock Pulse Generator (CPG) Usage Notes 4.8.1 Note on Crystal Resonator A sufficient evaluation at the user’s site is necessary to use the LSI, by referring the resonator connection examples shown in this section, because various characteristics related to the crystal resonator are closely linked to the user’s board design.
Page 90 Section 4 Clock Pulse Generator (CPG) A circuitry shown in figure 4.6 is recommended as an external circuitry around the PLL. Separate the PLL power lines (PLLVss) and the system power lines (Vcc, Vss) at the board power supply source, and be sure to insert bypass capacitors CB and CPB close to the pins. PLLV CPB = 0.1 µF * CB = 0.1 µF *...
Page 91: Section 5 Exception Handling
Section 5 Exception Handling Section 5 Exception Handling Overview 5.1.1 Types of Exception Handling and Priority Exception handling is started by four sources: resets, address errors, interrupts and instructions and have the priority, as shown in table 5.1. When several exceptions are detected at once, they are processed according to the priority.
Page 92: Exception Handling Operations
Section 5 Exception Handling 5.1.2 Exception Handling Operations The exceptions are detected and the exception handling starts according to the timing shown in table 5.2. Table 5.2 Timing for Exception Detection and Start of Exception Handling Exception Timing of Source Detection and Start of Exception Handling Started when the RES pin changes from low to high or when the Reset Power-on reset...
Page 93: Exception Handling Vector Table
Section 5 Exception Handling 5.1.3 Exception Handling Vector Table Before exception handling starts, the exception handling vector table must be set in memory. The exception handling vector table stores the start addresses of exception handling routines. (The reset exception handling table holds the initial values of PC and SP.) All exception sources are given different vector numbers and vector table address offsets.
Page 94 Section 5 Exception Handling Exception Handling Source Vector Number Vector Table Address Offset Interrupt IRQ0 (SH7125) H'00000100 to H'00000103 IRQ1 H'00000104 to H'00000107 IRQ2 H'00000108 to H'0000010B IRQ3 H'0000010C to H'0000010F (Reserved for system use) H'00000110 to H'00000113 H'0000011C to H'0000011F On-chip peripheral module* H'00000120 to H'00000123 H'000003FC to H'000003FF...
Page 95: Resets
Section 5 Exception Handling Resets 5.2.1 Types of Resets Resets have priority over any exception source. There are two types of resets: power-on resets and manual resets. As table 5.5 shows, both types of resets initialize the internal status of the CPU. In power-on resets, all registers of the on-chip peripheral modules are initialized;...
Page 96: Manual Reset
Section 5 Exception Handling 4. The values fetched from the exception handling vector table are set in PC and SP, then the program starts. Be certain to always perform power-on reset exception handling when turning the system power Power-On Reset by WDT: When WTCNT of the WDT overflows while a setting is made so that a power-on reset can be generated in watchdog timer mode of the WDT, this LSI enters the power-on reset state.
Page 97: Address Errors
Section 5 Exception Handling Address Errors 5.3.1 Address Error Sources Address errors occur when instructions are fetched or data is read from or written to, as shown in table 5.6. Table 5.6 Bus Cycles and Address Errors Bus Cycle Type Bus Master Bus Cycle Description Address Errors...
Page 98: Address Error Exception Source
Section 5 Exception Handling 5.3.2 Address Error Exception Source When an address error exception is generated, the bus cycle which caused the address error ends, the current instruction finishes, and then the address error exception handling starts. The CPU operates as follows: 1.
Page 99: Interrupts
Section 5 Exception Handling Interrupts 5.4.1 Interrupt Sources Table 5.7 shows the sources that start the interrupt exception handling. They are NMI, user break, IRQ, and on-chip peripheral modules. Table 5.7 Interrupt Sources Number of Sources Type Request Source NMI pin (external input) User break User break controller (UBC) IRQ0 to IRQ3 pins (external input)
Page 100: Interrupt Priority
Section 5 Exception Handling 5.4.2 Interrupt Priority The interrupt priority is predetermined. When multiple interrupts occur simultaneously (overlapped interruptions), the interrupt controller (INTC) determines their relative priorities and starts the exception handling according to the results. The priority of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and priority 16 the highest.
Page 101: Exceptions Triggered By Instructions
Section 5 Exception Handling Exceptions Triggered by Instructions 5.5.1 Types of Exceptions Triggered by Instructions Exception handling can be triggered by the trap instruction, illegal slot instructions, and general illegal instructions, as shown in table 5.9. Table 5.9 Types of Exceptions Triggered by Instructions Type Source Instruction Comment...
Page 102: Illegal Slot Instructions
Section 5 Exception Handling 5.5.3 Illegal Slot Instructions An instruction placed immediately after a delayed branch instruction is called "instruction placed in a delay slot". When the instruction placed in the delay slot is an undefined code, illegal slot exception handling starts after the undefined code is decoded. Illegal slot exception handling also starts when an instruction that changes the program counter (PC) value is placed in a delay slot and the instruction is decoded.
Page 103: Cases When Exceptions Are Accepted
Section 5 Exception Handling Cases when Exceptions are Accepted When an exception other than resets occurs during decoding the instruction placed in a delay slot or immediately after an interrupt disabled instruction, it may not be accepted and be held shown in table 5.10.
Page 104: Stack States After Exception Handling Ends
Section 5 Exception Handling Stack States after Exception Handling Ends The stack states after exception handling ends are shown in table 5.11. Table 5.11 Stack Status after Exception Handling Ends Types Stack State Address error (when the instruction that caused an exception is placed in Address of the delay slot) →...
Page 105 Section 5 Exception Handling Types Stack State Illegal slot instruction Address of → 32 bits delayed branch instruction 32 bits General illegal instruction Address of → 32 bits general illegal instruction 32 bits Rev. 3.00 Sep. 27, 2007 Page 85 of 758 REJ09B0243-0300...
Page 106: Usage Notes
Section 5 Exception Handling Usage Notes 5.8.1 Value of Stack Pointer (SP) The SP value must always be a multiple of 4. If it is not, an address error will occur when the stack is accessed during exception handling. 5.8.2 Value of Vector Base Register (VBR) The VBR value must always be a multiple of 4.
Page 107: Notes On Slot Illegal Instruction Exception Handling
Section 5 Exception Handling 5.8.4 Notes on Slot Illegal Instruction Exception Handling Some specifications on slot illegal instruction exception handling in this LSI differ from those of the conventional SH-2. • Conventional SH-2: Instructions LDC Rm,SR and LDC.L @Rm+,SR are not subject to the slot illegal instructions.
Page 108 Section 5 Exception Handling Rev. 3.00 Sep. 27, 2007 Page 88 of 758 REJ09B0243-0300...
Page 109: Section 6 Interrupt Controller (Intc)
Section 6 Interrupt Controller (INTC) Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. Features • 16 levels of interrupt priority • NMI noise canceller function • Occurrence of interrupt can be reported externally (IRQOUT pin) Rev.
Page 110 Section 6 Interrupt Controller (INTC) Figure 6.1 shows a block diagram of the INTC. IRQOUT IRQ0 Input IRQ1 control IRQ2 Com- IRQ3 parator Interrupt request I3 I2 I1 I0 (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) MTU2 (Interrupt request) (Interrupt request) (Interrupt request) ICR0...
Page 111: Input/Output Pins
Section 6 Interrupt Controller (INTC) Input/Output Pins Table 6.1 shows the INTC pin configuration. Table 6.1 Pin Configuration Name Abbr. Function Non-maskable interrupt input pin Input Input of non-maskable interrupt request signal Interrupt request input pins IRQ0 to Input Input of maskable interrupt request IRQ3 signals IRQOUT...
Page 112: Register Descriptions
Section 6 Interrupt Controller (INTC) Register Descriptions The interrupt controller has the following registers. For details on the addresses of these registers and the states of these registers in each processing state, see section 20, List of Registers. Table 6.2 Register Configuration Abbrevia- Register Name...
Page 113: Interrupt Control Register 0 (Icr0)
Section 6 Interrupt Controller (INTC) 6.3.1 Interrupt Control Register 0 (ICR0) ICR0 is a 16-bit register that sets the input signal detection mode of the external interrupt input pin NMI and indicates the input signal level on the NMI pin. Bit: NMIL NMIE...
Page 114: Irq Control Register (Irqcr)
Section 6 Interrupt Controller (INTC) 6.3.2 IRQ Control Register (IRQCR) IRQCR is a 16-bit register that sets the input signal detection mode of the external interrupt input pins IRQ0 to IRQ3. Bit: IRQ31S IRQ30S IRQ21S IRQ20S IRQ11S IRQ10S IRQ01S IRQ00S Initial value: R/W: Initial...
Page 115 Section 6 Interrupt Controller (INTC) Initial Value Bit Name Description IRQ11S IRQ1 Sense Select IRQ10S Set the interrupt request detection mode for pin IRQ1. 00: Interrupt request is detected at the low level of pin IRQ1 01: Interrupt request is detected at the falling edge of pin IRQ1 10: Interrupt request is detected at the rising edge of pin IRQ1...
Page 116: Irq Status Register (Irqsr)
Section 6 Interrupt Controller (INTC) 6.3.3 IRQ Status register (IRQSR) IRQSR is a 16-bit register that indicates the states of the external interrupt input pins IRQ0 to IRQ3 and the status of interrupt request. Bit: IRQ3L IRQ2L IRQ1L IRQ0L IRQ3F IRQ2F IRQ1F IRQ0F Initial value: R/W: Note:...
Page 117 Section 6 Interrupt Controller (INTC) Initial Value Bit Name Description IRQ3F Indicates the status of an IRQ3 interrupt request. • When level detection mode is selected 0: An IRQ3 interrupt has not been detected [Clearing condition] Driving pin IRQ3 high 1: An IRQ3 interrupt has been detected [Setting condition] Driving pin IRQ3 low...
Page 118 Section 6 Interrupt Controller (INTC) Initial Value Bit Name Description IRQ2F Indicates the status of an IRQ2 interrupt request. • When level detection mode is selected 0: An IRQ2 interrupt has not been detected [Clearing condition] Driving pin IRQ2 high 1: An IRQ2 interrupt has been detected [Setting condition] Driving pin IRQ2 low...
Page 119: Interrupt Priority Registers A To F And H To M (Ipra To Iprf And Iprh To Iprm)
Section 6 Interrupt Controller (INTC) Initial Value Bit Name Description IRQ0F Indicates the status of an IRQ0 interrupt request. • When level detection mode is selected 0: An IRQ0 interrupt has not been detected [Clearing condition] Driving pin IRQ0 high 1: An IRQ0 interrupt has been detected [Setting condition] Driving pin IRQ0 low...
Page 120 Section 6 Interrupt Controller (INTC) Initial Value Bit Name Description 15 to 12 IPR[15:12] 0000 Set priority levels for the corresponding interrupt source. 0000: Priority level 0 (lowest) 0001: Priority level 1 0010: Priority level 2 0011: Priority level 3 0100: Priority level 4 0101: Priority level 5 0110: Priority level 6...
Page 121 Section 6 Interrupt Controller (INTC) Initial Value Bit Name Description 7 to 4 IPR[7:4] 0000 Set priority levels for the corresponding interrupt source. 0000: Priority level 0 (lowest) 0001: Priority level 1 0010: Priority level 2 0011: Priority level 3 0100: Priority level 4 0101: Priority level 5 0110: Priority level 6...
Page 122: Interrupt Sources
Section 6 Interrupt Controller (INTC) Interrupt Sources 6.4.1 External Interrupts There are four types of interrupt sources: User break, NMI, IRQ, and on-chip peripheral modules. Individual interrupts are given priority levels (0 to 16, with 0 the lowest and 16 the highest). Giving an interrupt a priority level of 0 masks it.
Page 123: On-Chip Peripheral Module Interrupts
Section 6 Interrupt Controller (INTC) IRQSR.IRQnL IRQCR.IRQn1S IRQSR.IRQnF IRQCR.IRQn0S Level IRQn pins detection CPU interrupt request Edge detection RESIRQn (Acceptance of IRQn interrupt/ writing 0 after reading IRQnF = 1) n = 3 to 0 Figure 6.2 Block Diagram of IRQ3 to IRQ0 Interrupts Control 6.4.2 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral...
Page 124: Interrupt Exception Handling Vector Table
Section 6 Interrupt Controller (INTC) Interrupt Exception Handling Vector Table Table 6.3 lists interrupt sources, their vector numbers, vector table address offsets, and interrupt priorities. Individual interrupt sources are allocated to different vector numbers and vector table address offsets. Vector table addresses are calculated from the vector numbers and vector table address offsets.
Page 125 Section 6 Interrupt Controller (INTC) Table 6.3 Interrupt Exception Handling Vectors and Priorities Interrupt Vector Vector Table Default Source Starting Address IPR Priority Name  User break H'00000030 High  External pin H'0000002C IRQ0 (only SH7125) 64 H'00000100 IPRA15 to IPRA12 IRQ1 H'00000104 IPRA11 to IPRA8...
Page 126 Section 6 Interrupt Controller (INTC) Interrupt Vector Vector Table Default Source Starting Address IPR Priority Name MTU2_4 TGIA_4 H'000001E0 IPRF15 to IPRF12 High TGIB_4 H'000001E4 TGIC_4 H'000001E8 TGID_4 H'000001EC TCIV_4 H'000001F0 IPRF11 to IPRF8 MTU2_5 TGIU_5 H'00000200 IPRF7 to IPRF4 TGIV_5 H'00000204 TGIW_5...
Page 127: Interrupt Operation
Section 6 Interrupt Controller (INTC) Interrupt Operation 6.6.1 Interrupt Sequence The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest priority interrupt from interrupt requests sent, according to the priority levels set in interrupt priority registers A to F and H to M (IPRA to IPRF and IPRH to IPRM).
Page 128 Section 6 Interrupt Controller (INTC) Notes: The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt source that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, confirm that it has been cleared, and then execute an RTE instruction.
Page 129 Section 6 Interrupt Controller (INTC) Program execution state Interrupt? User break? NMI? Level 15 interrupt? Level 14 interrupt? I3 to I0 I3 to I0 level 14? level 14? Level 1 interrupt? I3 to I0 level 13? I3 to I0 level 0? IRQOUT = low Save SR to stack Save PC to stack...
Page 130: Stack After Interrupt Exception Handling
Section 6 Interrupt Controller (INTC) 6.6.2 Stack after Interrupt Exception Handling Figure 6.4 shows the stack after interrupt exception handling. Address 32 bits 4n – 8 32 bits 4n – 4 Notes: 1. PC is the start address of the next instruction (instruction at the return address) after the executed instruction.
Page 131 Section 6 Interrupt Controller (INTC) Table 6.4 Interrupt Response Time Number of Cycles Peripheral Item Modules Remarks 1 × Icyc + 2 × 1 × Icyc + 1 × 1 × Icyc + 2 × Interrupt priority decision and comparison with mask Pcyc Pcyc Pcyc...
Page 132: Usage Note
Section 6 Interrupt Controller (INTC) Usage Note The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt source that should have been cleared is not inadvertently accepted again, read the interrupt source flag after it has been cleared, confirm that it has been cleared, and then execute an RTE instruction.
Page 133: Section 7 User Break Controller (Ubc)
Section 7 User Break Controller (UBC) Section 7 User Break Controller (UBC) The user break controller (UBC) provides functions that simplify program debugging. These functions make it easy to design an effective self-monitoring debugger, enabling the chip to debug programs without using an in-circuit emulator. Break conditions that can be set in the UBC are instruction fetch or data read/write access, data size, data contents, address value, and stop timing in the case of instruction fetch.
Page 134 Section 7 User Break Controller (UBC) Figure 7.1 shows a block diagram of the UBC. Access Internal bus control Access BBRA comparator BARA Address comparator BAMRA BDRA Data comparator BDMRA Channel A Access BBRB comparator BARB Address BAMRB comparator BDRB Data comparator BDMRB...
Page 135: Register Descriptions
Section 7 User Break Controller (UBC) Register Descriptions The user break controller has the following registers. For details on register addresses and register states during each processing, refer to section 20, List of Registers. Table 7.1 Register Configuration Abbrevia- Register Name tion Initial Value Address...
Page 136: Break Address Register A (Bara)
Section 7 User Break Controller (UBC) 7.2.1 Break Address Register A (BARA) BARA is a 32-bit readable/writable register. BARA specifies the address used as a break condition in channel A. Bit: BAA31 BAA30 BAA29 BAA28 BAA27 BAA26 BAA25 BAA24 BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 Initial value: R/W: Bit:...
Page 137: Break Bus Cycle Register A (Bbra)
Section 7 User Break Controller (UBC) Initial Value Bit Name Description 31 to 0 BAMA31 to All 0 Break Address Mask A BAMA 0 Specify bits masked in the channel A break address bits specified by BARA (BAA31 to BAA0). 0: Break address bit BAAn of channel A is included in the break condition 1: Break address bit BAAn of channel A is masked and...
Page 138 Section 7 User Break Controller (UBC) Initial Value Bit Name Description 7, 6 CDA[1:0] L Bus Cycle/I Bus Cycle Select A Select the L bus cycle or I bus cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the L bus cycle 10: The break condition is the I bus cycle...
Page 139: Break Data Register A (Bdra)
Section 7 User Break Controller (UBC) 7.2.4 Break Data Register A (BDRA) BDRA is a 32-bit readable/writable register. The control bits CDA1 and CDA0 in BBRA select one of two data buses for break condition A. Bit: BDA31 BDA30 BDA29 BDA28 BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16 Initial value: R/W: Bit:...
Page 140: Break Data Mask Register A (Bdmra)
Section 7 User Break Controller (UBC) 7.2.5 Break Data Mask Register A (BDMRA) BDMRA is a 32-bit readable/writable register. BDMRA specifies bits masked in the break data specified by BDRA. Bit: BDMA31 BDMA30 BDMA29 BDMA28 BDMA27 BDMA26 BDMA25 BDMA24 BDMA23 BDMA22 BDMA21 BDMA20 BDMA19 BDMA18 BDMA17 BDMA16 Initial value: R/W: Bit:...
Page 141: Break Address Register B (Barb)
Section 7 User Break Controller (UBC) 7.2.6 Break Address Register B (BARB) BARB is a 32-bit readable/writable register. BARB specifies the address used as a break condition in channel B. Control bits CDB1 and CDB0 in BBRB select one of the two address buses for break condition B.
Page 142: Break Address Mask Register B (Bamrb)
Section 7 User Break Controller (UBC) 7.2.7 Break Address Mask Register B (BAMRB) BAMRB is a 32-bit readable/writable register. BAMRB specifies bits masked in the break address specified by BARB. Bit: BAMB31 BAMB30 BAMB29 BAMB28 BAMB27 BAMB26 BAMB25 BAMB24 BAMB23 BAMB22 BAMB21 BAMB20 BAMB19 BAMB18 BAMB17 BAMB16 Initial value: R/W: Bit:...
Page 143: Break Data Register B (Bdrb)
Section 7 User Break Controller (UBC) 7.2.8 Break Data Register B (BDRB) BDRB is a 32-bit readable/writable register. The control bits CDB1 and CDB0 in BBRB select one of the two data buses for break condition B. Bit: BDB31 BDB30 BDB29 BDB28 BDB27 BDB26 BDB25 BDB24 BDB23 BDB22 BDB21 BDB20 BDB19 BDB18 BDB17 BDB16 Initial value: R/W: Bit:...
Page 144: Break Data Mask Register B (Bdmrb)
Section 7 User Break Controller (UBC) 7.2.9 Break Data Mask Register B (BDMRB) BDMRB is a 32-bit readable/writable register. BDMRB specifies bits masked in the break data specified by BDRB. Bit: BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16 Initial value: R/W: Bit:...
Page 145: Break Bus Cycle Register B (Bbrb)
Section 7 User Break Controller (UBC) 7.2.10 Break Bus Cycle Register B (BBRB) BBRB is a 16-bit readable/writable register, which specifies (1) bus master for I bus cycle, (2) L bus cycle or I bus cycle, (3) instruction fetch or data access, (4) read or write, and (5) operand size in the break conditions of channel B.
Page 146 Section 7 User Break Controller (UBC) Initial Value Bit Name Description 5, 4 IDB[1:0] Instruction Fetch/Data Access Select B Select the instruction fetch cycle or data access cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle 11: The break condition is the instruction fetch cycle or...
Page 147: Break Control Register (Brcr)
Section 7 User Break Controller (UBC) 7.2.11 Break Control Register (BRCR) BRCR sets the following conditions: 1. Channels A and B are used in two independent channel conditions or under the sequential condition. 2. A break is set before or after instruction execution. 3.
Page 148 Section 7 User Break Controller (UBC) Initial Value Bit Name Description  Reserved This bit is always read as 0. The write value should always be 0. UBIDA User Break Disable A Enables or disables the user break interrupt request when the channel A break conditions are satisfied.
Page 149 Section 7 User Break Controller (UBC) Initial Value Bit Name Description SCMFDB I Bus Cycle Condition Match Flag B When the I bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1. In order to clear this flag, write 0 into this bit.
Page 150 Section 7 User Break Controller (UBC) Initial Value Bit Name Description DBEB Data Break Enable B Selects whether or not the data bus condition is included in the break condition of channel B. 0: No data bus condition is included in the condition of channel B 1: The data bus condition is included in the condition of channel B...
Page 151: Execution Times Break Register (Betr)
Section 7 User Break Controller (UBC) 7.2.12 Execution Times Break Register (BETR) BETR is a 16-bit readable/writable register. When the execution-times break condition of channel B is enabled, this register specifies the number of execution times to make the break. The maximum number is 2 –...
Page 152: Branch Source Register (Brsr)
Section 7 User Break Controller (UBC) 7.2.13 Branch Source Register (BRSR) BRSR is a 32-bit read-only register. BRSR stores bits 27 to 0 in the address of the branch source instruction. BRSR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 by a power-on reset or manual reset when BRSR is read or the setting to enable PC trace is made.
Page 153: Branch Destination Register (Brdr)
Section 7 User Break Controller (UBC) 7.2.14 Branch Destination Register (BRDR) BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is cleared to 0 by a power-on reset or manual reset when BRDR is read or the setting to enable PC trace is made.
Page 154: Operation
Section 7 User Break Controller (UBC) Operation 7.3.1 Flow of the User Break Operation The flow from setting of break conditions to user break exception processing is described below: 1. The break addresses are set in the break address registers (BARA or BARB). The masked addresses are set in the break address mask registers (BAMRA or BAMRB).
Page 155: Break On Instruction Fetch Cycle
Section 7 User Break Controller (UBC) 7.3.2 Break on Instruction Fetch Cycle 1. When L bus/instruction fetch/read/word, longword, or not including the operand size is set in the break bus cycle register (BBRA or BBRB), the break condition becomes the L bus instruction fetch cycle.
Page 156 Section 7 User Break Controller (UBC) Table 7.2 Data Access Cycle Addresses and Operand Size Comparison Conditions Access Size Address Compared Longword Compares break address register bits 31 to 2 to address bus bits 31 to 2 Word Compares break address register bits 31 to 1 to address bus bits 31 to 1 Byte Compares break address register bits 31 to 0 to address bus bits 31 to 0 This means that when address H'00001003 is set in the break address register (BARA or...
Page 157: Sequential Break
Section 7 User Break Controller (UBC) 7.3.4 Sequential Break 1. By setting the SEQ bit in BRCR to 1, the sequential break is issued when a channel B break condition matches after a channel A break condition matches. A user break is not generated even if a channel B break condition matches before a channel A break condition matches.
Page 158: Pc Trace
Section 7 User Break Controller (UBC) 4. When data access (address + data) is specified as a break condition: When a data value is added to the break conditions, the address of an instruction that is within two instructions of the instruction that matched the break condition is saved in the stack. At which instruction the break occurs cannot be determined accurately.
Page 159: Usage Examples
Section 7 User Break Controller (UBC) 7.3.7 Usage Examples Break Condition Specified for L Bus Instruction Fetch Cycle: (Example 1-1) • Register specifications BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BDRA = H'00000000, BDMRA = H'00000000, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400 Specified conditions: Channel A/channel B independent mode <Channel A>...
Page 160 Section 7 User Break Controller (UBC) <Channel B> Address: H'0003722E, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/word After an instruction with address H'00037226 is executed, a user break occurs before an instruction with address H'0003722E is executed.
Page 161 Section 7 User Break Controller (UBC) <Channel B> Address: H'0003722E, Address mask: H'00000000 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read/word Since instruction fetch is not a write cycle on channel A, a sequential condition does not match.
Page 162 Section 7 User Break Controller (UBC) Bus cycle: L bus/instruction fetch (after instruction execution)/read (operand size is not included in the condition) <Channel B> Address: H'00008010, Address mask: H'00000006 Data: H'00000000, Data mask: H'00000000 Bus cycle: L bus/instruction fetch (before instruction execution)/read (operand size is not included in the condition) A user break occurs after an instruction with addresses H'00008000 to H'00008FFE is executed or before an instruction with addresses H'00008010 to H'00008016 are executed.
Page 163 Section 7 User Break Controller (UBC) Break Condition Specified for I Bus Data Access Cycle: (Example 3-1) • Register specifications BARA = H'00314154, BAMRA = H'00000000, BBRA = H'0194, BDRA = H'12345678, BDMRA = H'FFFFFFFF, BARB = H'00055555, BAMRB = H'00000000, BBRB = H'01A9, BDRB = H'00007878, BDMRB = H'00000F0F, BRCR = H'00000080 Specified conditions: Channel A/channel B independent mode <Channel A>...
Page 164: Usage Notes
Section 7 User Break Controller (UBC) Usage Notes 1. The CPU can read from or write to the UBC registers via the I bus. Accordingly, during the period from executing an instruction to rewrite the UBC register till the new value is actually rewritten, the desired break may not occur.
Page 165 Section 7 User Break Controller (UBC) 8. Do not set a post-execution break at a SLEEP instruction or a branch instruction for which a SLEEP instruction is placed in the delay slot. In addition, do not set a data access break at a SLEEP instruction or one or two instructions before a SLEEP instruction.
Page 166 Section 7 User Break Controller (UBC) Rev. 3.00 Sep. 27, 2007 Page 146 of 758 REJ09B0243-0300...
Page 167: Section 8 Bus State Controller (Bsc)
Section 8 Bus State Controller (BSC) Section 8 Bus State Controller (BSC) The bus state controller (BSC) controls data transmission and reception between the internal buses (L bus, I bus, and peripheral bus) and also controls the CPU’s access to the on-chip FLASH, on- chip RAM, and on-chip peripheral I/O.
Page 168: Access To On-Chip Peripheral I/O Register
Section 8 Bus State Controller (BSC) Access to the on-chip RAM for read/write is synchronized with I φ clock and is executed in one clock cycle. For details, see section 18, RAM. Access to on-chip Peripheral I/O Register The on-chip peripheral I/O register is accessed by the bus state controller (BSC) as described in table 8.2.
Page 169 Section 8 Bus State Controller (BSC) Iclk L bus Bclk I bus Pclk Peripheral bus Figure 8.1 Timing of Write Access to the Peripheral Bus (Iclk:Bclk:Pclk = 4:1:1) Figure 8.2 shows an example of timing of write access to the peripheral bus when Iclk:Bclk:Pclk = 4:4:1.
Page 170 Section 8 Bus State Controller (BSC) period is required because Iclk ≥ Bclk ≥ Pclk. In the case shown in figure 8.3, where n = 0 and m = 1, the period required for access by the CPU is 3 × Iclk + 2 × Bclk + 2 × Pclk + 2 × Iclk. Iclk L bus Bclk...
Page 171: Section 9 Multi-Function Timer Pulse Unit 2 (Mtu2)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) This LSI has an on-chip multi-function timer pulse unit 2 (MTU2) that comprises six 16-bit timer channels. Features • Maximum 16 (SH7125) or 12 (SH7124) pulse input/output lines and three pulse input lines •...
Page 172 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.1 MTU2 Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 MPφ/1 MPφ/1 MPφ/1 Count clock MPφ/1 MPφ/1 MPφ/1 MPφ/4 MPφ/4 MPφ/4 MPφ/4 MPφ/4 MPφ/4 MPφ/16 MPφ/16 MPφ/16 MPφ/16...
Page 173 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 √ √ Phase counting — — — — mode √ √ √ Buffer operation — — — √ Dead time —...
Page 174 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Interrupt sources 7 sources 4 sources 4 sources 5 sources 5 sources 3 sources • • • • • •...
Page 175 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 • A/D converter start — — — — — request delaying converter function start request at a match between TADCOR A_4 and TCNT_4...
Page 176 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Figure 9.1 shows a block diagram of the MTU2. Interrupt request signals Channel 3: TGIA_3 TGIB_3 Input/output pins TGIC_3 Channel 3: TIOC3A TGID_3 TIOC3B TCIV_3 TIOC3C Channel 4: TGIA_4 TIOC3D TGIB_4 Channel 4: TIOC4A TGIC_4 TIOC4B TGID_4...
Page 177: Input/Output Pins
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Input/Output Pins Table 9.2 Pin Configuration Channel Pin Name I/O Function Common TCLKA Input External clock A input pin (Channel 1 phase counting mode A phase input) TCLKB Input External clock B input pin (Channel 1 phase counting mode B phase input) TCLKC Input External clock C input pin...
Page 178: Register Descriptions
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Register Descriptions The MTU2 has the following registers. For details on register addresses and register states during each process, see section 20, List of Registers. To distinguish registers in each channel, an underscore and the channel number are added as a suffix to the register name;...
Page 179 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Abbrevia- Register Name tion Initial value Address Access Size Timer subcounter TCNTS H'0000 H'FFFFC220 16, 32 Timer cycle buffer register TCBR H'FFFF H'FFFFC222 Timer general register C_3 TGRC_3 H'FFFF H'FFFFC224 16, 32 Timer general register D_3 TGRD_3 H'FFFF...
Page 180 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Abbrevia- Register Name tion Initial value Address Access Size Timer waveform control TWCR H'00 H'FFFFC260 register Timer start register TSTR H'00 H'FFFFC280 8, 16 Timer synchronous register TSYR H'00 H'FFFFC281 Timer counter synchronous TCSYSTR H'00 H'FFFFC282...
Page 181 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Abbrevia- Register Name tion Initial value Address Access Size Timer counter_1 TCNT_1 H'0000 H'FFFFC386 Timer general register A_1 TGRA_1 H'FFFF H'FFFFC388 16, 32 Timer general register B_1 TGRB_1 H'FFFF H'FFFFC38A Timer input capture control TICCR H'00 H'FFFFC390...
Page 182: Timer Control Register (Tcr)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.1 Timer Control Register (TCR) The TCR registers are 8-bit readable/writable registers that control the TCNT operation for each channel. The MTU2 has a total of eight TCR registers, one each for channels 0 to 4 and three (TCRU_5, TCRV_5, and TCRW_5) for channel 5.
Page 183 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.4 CCLR0 to CCLR2 (Channels 0, 3, and 4) Bit 7 Bit 6 Bit 5 Channel CCLR2 CCLR1 CCLR0 Description 0, 3, 4 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture...
Page 184 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.6 TPSC0 to TPSC2 (Channel 0) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on MPφ/1 Internal clock: counts on MPφ/4 Internal clock: counts on MPφ/16 Internal clock: counts on MPφ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input...
Page 185 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.8 TPSC0 to TPSC2 (Channel 2) Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on MPφ/1 Internal clock: counts on MPφ/4 Internal clock: counts on MPφ/16 Internal clock: counts on MPφ/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input...
Page 186: Timer Mode Register (Tmdr)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.10 TPSC1 and TPSC0 (Channel 5) Bit 1 Bit 0 Channel TPSC1 TPSC0 Description Internal clock: counts on MPφ/1 Internal clock: counts on MPφ/4 Internal clock: counts on MPφ/16 Internal clock: counts on MPφ/64 Note: Bits 7 to 2 are reserved in channel 5.
Page 187 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Value Bit Name Description Buffer Operation B Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare do not take place in modes other than complementary PWM mode, but compare match with TGRD occurs in...
Page 188 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.11 Setting of Operation Mode by Bits MD0 to MD3 Bit 3 Bit 2 Bit 1 Bit 0 Description Normal operation Setting prohibited PWM mode 1 PWM mode 2* Phase counting mode 1* Phase counting mode 2* Phase counting mode 3* Phase counting mode 4*...
Page 189: Timer I/O Control Register (Tior)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.3 Timer I/O Control Register (TIOR) The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU2 has a total of eleven TIOR registers, two each for channels 0, 3, and 4, one each for channels 1 and 2, and three (TIORU_5, TIORV_5, and TIORW_5) for channel 5.
Page 190 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) • TIORL_0, TIORL_3, TIORL_4 Bit: IOD[3:0] IOC[3:0] Initial value: R/W: Initial Bit Name Value Description 7 to 4 IOD[3:0] 0000 I/O Control D0 to D3 Specify the function of TGRD. See the following tables. TIORL_0: Table 9.13 TIORL_3: Table 9.17 TIORL_4: Table 9.19...
Page 191 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.12 TIORH_0 (Channel 0) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_0 IOB3 IOB2 IOB1 IOB0 Function TIOC0B Pin Function Output Output retained* compare Initial output is 0 register 0 output at compare match Initial output is 0 1 output at compare match...
Page 192 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.13 TIORL_0 (Channel 0) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRD_0 IOD3 IOD2 IOD1 IOD0 Function TIOC0D Pin Function Output Output retained* compare Initial output is 0 register* 0 output at compare match Initial output is 0 1 output at compare match...
Page 193 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.14 TIOR_1 (Channel 1) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_1 IOB3 IOB2 IOB1 IOB0 Function TIOC1B Pin Function* Output Output retained* compare Initial output is 0 register 0 output at compare match Initial output is 0 1 output at compare match...
Page 194 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.15 TIOR_2 (Channel 2) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_2 IOB3 IOB2 IOB1 IOB0 Function TIOC2B Pin Function* Output Output retained* compare Initial output is 0 register 0 output at compare match Initial output is 0 1 output at compare match...
Page 195 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.16 TIORH_3 (Channel 3) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_3 IOB3 IOB2 IOB1 IOB0 Function TIOC3B Pin Function Output Output retained* compare Initial output is 0 register 0 output at compare match Initial output is 0 1 output at compare match...
Page 196 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.17 TIORL_3 (Channel 3) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRD_3 IOD3 IOD2 IOD1 IOD0 Function TIOC3D Pin Function Output Output retained* compare Initial output is 0 register* 0 output at compare match Initial output is 0 1 output at compare match...
Page 197 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.18 TIORH_4 (Channel 4) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRB_4 IOB3 IOB2 IOB1 IOB0 Function TIOC4B Pin Function Output Output retained* compare Initial output is 0 register 0 output at compare match Initial output is 0 1 output at compare match...
Page 198 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.19 TIORL_4 (Channel 4) Description Bit 7 Bit 6 Bit 5 Bit 4 TGRD_4 IOD3 IOD2 IOD1 IOD0 Function TIOC4D Pin Function Output Output retained* compare Initial output is 0 register* 0 output at compare match Initial output is 0 1 output at compare match...
Page 199 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.20 TIORH_0 (Channel 0) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_0 IOA3 IOA2 IOA1 IOA0 Function TIOC0A Pin Function Output Output retained* compare Initial output is 0 register 0 output at compare match Initial output is 0 1 output at compare match...
Page 200 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.21 TIORL_0 (Channel 0) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRC_0 IOC3 IOC2 IOC1 IOC0 Function TIOC0C Pin Function Output Output retained* compare Initial output is 0 register* 0 output at compare match Initial output is 0 1 output at compare match...
Page 201 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.22 TIOR_1 (Channel 1) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_1 IOA3 IOA2 IOA1 IOA0 Function TIOC1A Pin Function* Output Output retained* compare Initial output is 0 register 0 output at compare match Initial output is 0 1 output at compare match...
Page 202 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.23 TIOR_2 (Channel 2) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_2 IOA3 IOA2 IOA1 IOA0 Function TIOC2A Pin Function* Output Output retained* compare Initial output is 0 register 0 output at compare match Initial output is 0 1 output at compare match...
Page 203 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.24 TIORH_3 (Channel 3) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_3 IOA3 IOA2 IOA1 IOA0 Function TIOC3A Pin Function Output Output retained* compare Initial output is 0 register 0 output at compare match Initial output is 0 1 output at compare match...
Page 204 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.25 TIORL_3 (Channel 3) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRC_3 IOC3 IOC2 IOC1 IOC0 Function TIOC3C Pin Function Output Output retained* compare Initial output is 0 register* 0 output at compare match Initial output is 0 1 output at compare match...
Page 205 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.26 TIORH_4 (Channel 4) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRA_4 IOA3 IOA2 IOA1 IOA0 Function TIOC4A Pin Function Output Output retained* compare Initial output is 0 register 0 output at compare match Initial output is 0 1 output at compare match...
Page 206 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.27 TIORL_4 (Channel 4) Description Bit 3 Bit 2 Bit 1 Bit 0 TGRC_4 IOC3 IOC2 IOC1 IOC0 Function TIOC4C Pin Function Output Output retained* compare Initial output is 0 register* 0 output at compare match Initial output is 0 1 output at compare match...
Page 207 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.28 TIORU_5, TIORV_5, and TIORW_5 (Channel 5) Description TGRU_5, TGRV_5, and Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TGRW_5 IOC4 IOC3 IOC2 IOC1 IOC0 Function TIC5U, TIC5V, and TIC5W Pin Function Compare Compare match match register...
Page 208: Timer Compare Match Clear Register (Tcntcmpclr)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.4 Timer Compare Match Clear Register (TCNTCMPCLR) TCNTCMPCLR is an 8-bit readable/writable register that specifies requests to clear TCNTU_5, TCNTV_5, and TCNTW_5. The MTU2 has one TCNTCMPCLR in channel 5. Bit: CLR5U CLR5V CLR5W Initial value:...
Page 209: Timer Interrupt Enable Register (Tier)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Value Bit Name Description CMPCLR5W 0 TCNT Compare Clear 5W Enables or disables requests to clear TCNTW_5 at TGRW_5 compare match or input capture. 0: Disables TCNTW_5 to be cleared to H'0000 at TCNTW_5 and TGRW_5 compare match or input capture 1: Enables TCNTW_5 to be cleared to H'0000 at...
Page 210 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Value Bit Name Description TTGE2 A/D Converter Start Request Enable 2 Enables or disables generation of A/D converter start requests by TCNT_4 underflow (trough) in complementary PWM mode. In channels 0 to 3, bit 6 is reserved. It is always read as 0 and the write value should always be 0.
Page 211 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Value Bit Name Description TGIEC TGR Interrupt Enable C Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0, 3, and 4. In channels 1 and 2, bit 2 is reserved.
Page 212 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) • TIER2_0 Bit: TTGE2 TGIEF TGIEE Initial value: R/W: Initial Bit Name Value Description TTGE2 A/D Converter Start Request Enable 2 Enables or disables generation of A/D converter start requests by compare match between TCNT_0 and TGRE_0.
Page 213 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) • TIER_5 Bit: TGIE5U TGIE5V TGIE5W Initial value: R/W: Initial Bit Name Value Description 7 to 3 — All 0 Reserved These bits are always read as 0. The write value should always be 0.
Page 214: Timer Status Register (Tsr)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.6 Timer Status Register (TSR) The TSR registers are 8-bit readable/writable registers that indicate the status of each channel. The MTU2 has seven TSR registers, two for channel 0 and one each for channels 1 to 5. •...
Page 215 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Value Bit Name Description TCFV R/(W)* Overflow Flag Status flag that indicates that TCNT overflow has occurred. Only 0 can be written, for flag clearing. [Setting condition] • When the TCNT value overflows (changes from H'FFFF to H'0000) In channel 4, when the TCNT_4 value underflows (changes from H'0001 to H'0000) in complementary...
Page 216 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Value Bit Name Description TGFC R/(W)* Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0, 3, and 4. Only 0 can be written, for flag clearing. In channels 1 and 2, bit 2 is reserved.
Page 217 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Value Bit Name Description TGFA R/(W)* Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. Only 0 can be written, for flag clearing. [Setting conditions] •...
Page 218 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) • TSR2_0 Bit: TGFF TGFE Initial value: R/W: R/(W)* R/(W)* Note: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Initial Value Bit Name Description 7, 6...
Page 219 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) • TSR_5 Bit: CMFU5 CMFV5 CMFW5 Initial value: R/W: R/(W)* R/(W)* R/(W)* Note: Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. Initial Value Bit Name...
Page 220 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Value Bit Name Description CMFV5 R/(W)* Compare Match/Input Capture Flag V5 Status flag that indicates the occurrence of TGRV_5 input capture or compare match. [Setting conditions] • When TCNTV_5 = TGRV_5 and TGRV_5 is functioning as output compare register •...
Page 221 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Value Bit Name Description CMFW5 R/(W)* Compare Match/Input Capture Flag W5 Status flag that indicates the occurrence of TGRW_5 input capture or compare match. [Setting conditions] • When TCNTW_5 = TGRW_5 and TGRW_5 is functioning as output compare register •...
Page 222: Timer Buffer Operation Transfer Mode Register (Tbtm)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.7 Timer Buffer Operation Transfer Mode Register (TBTM) The TBTM registers are 8-bit readable/writable registers that specify the timing for transferring data from the buffer register to the timer general register in PWM mode. The MTU2 has three TBTM registers, one each for channels 0, 3, and 4.
Page 223: Timer Input Capture Control Register (Ticcr)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Value Bit Name Description TTSA Timing Select A Specifies the timing for transferring data from TGRC to TGRA in each channel when they are used together for buffer operation. When using channel 0 in other than PWM mode, do not set this bit to 1.
Page 224 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Value Bit Name Description I2AE Input Capture Enable Specifies whether to include the TIOC2A pin in the TGRA_1 input capture conditions. 0: Does not include the TIOC2A pin in the TGRA_1 input capture conditions 1: Includes the TIOC2A pin in the TGRA_1 input capture conditions...
Page 225: Timer A/D Converter Start Request Control Register (Tadcr)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.9 Timer A/D Converter Start Request Control Register (TADCR) TADCR is a 16-bit readable/writable register that enables or disables A/D converter start requests and specifies whether to link A/D converter start requests with interrupt skipping operation. The MTU2 has one TADCR in channel 4.
Page 226 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Value Bit Name Description UT4BE Up-Count TRG4BN Enable Enables or disables A/D converter start requests (TRG4BN) during TCNT_4 up-count operation. 0: A/D converter start requests (TRG4BN) disabled during TCNT_4 up-count operation 1: A/D converter start requests (TRG4BN) enabled during TCNT_4 up-count operation DT4BE...
Page 227 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Value Bit Name Description ITB4VE TCIV_4 Interrupt Skipping Link Enable Select whether to link A/D converter start requests (TRG4BN) with TCIV_4 interrupt skipping operation. 0: Does not link with TCIV_4 interrupt skipping 1: Links with TCIV_4 interrupt skipping Notes: 1.
Page 228: Timer A/D Converter Start Request Cycle Set Registers
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.10 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and TADCORB_4) TADCORA_4 and TADCORB_4 are 16-bit readable/writable registers. When the TCNT_4 count reaches the value in TADCORA_4 or TADCORB_4, a corresponding A/D converter start request will be issued.
Page 229: Timer Counter (Tcnt)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.12 Timer Counter (TCNT) The TCNT counters are 16-bit readable/writable counters. The MTU2 has eight TCNT counters, one each for channels 0 to 4 and three (TCNTU_5, TCNTV_5, and TCNTW_5) for channel 5. The TCNT counters are initialized to H'0000 by a reset.
Page 230: Timer Start Register (Tstr)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.14 Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that selects operation/stoppage of TCNT for channels 0 to 4. TSTR_5 is an 8-bit readable/writable register that selects operation/stoppage of TCNTU_5, TCNTV_5, and TCNTW_5 for channel 5.
Page 231 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Value Bit Name Description CST2 Counter Start 2 to 0 These bits select operation or stoppage for TCNT. CST1 If 0 is written to the CST bit during operation with the CST0 TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained.
Page 232: Timer Synchronous Register (Tsyr)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.15 Timer Synchronous Register (TSYR) TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
Page 233 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Value Bit Name Description SYNC2 Timer Synchronous operation 2 to 0 These bits are used to select whether operation is SYNC1 independent of or synchronized with other channels. SYNC0 When synchronous operation is selected, the TCNT synchronous presetting of multiple channels, and synchronous clearing by counter clearing on another channel, are possible.
Page 234: Timer Counter Synchronous Start Register (Tcsystr)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.16 Timer Counter Synchronous Start Register (TCSYSTR) TCSYSTR is an 8-bit readable/writable register that specifies synchronous start of the MTU2 counters. Bit: SCH0 SCH1 SCH2 SCH3 SCH4 Initial value: R/W: R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: Only 1 can be written to set the register.
Page 235 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Value Bit Name Description SCH2 R/(W)* Synchronous Start Controls synchronous start of TCNT_2 in the MTU2. 0: Does not specify synchronous start for TCNT_2 in the MTU2 1: Specifies synchronous start for TCNT_2 in the MTU2 [Clearing condition] •...
Page 236: Timer Read/Write Enable Register (Trwer)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.17 Timer Read/Write Enable Register (TRWER) TRWER is an 8-bit readable/writable register that enables or disables access to the registers and counters which have write-protection capability against accidental modification in channels 3 and Bit: Initial value: R/W:...
Page 237: Timer Output Master Enable Register (Toer)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.18 Timer Output Master Enable Register (TOER) TOER is an 8-bit readable/writable register that enables/disables output settings for output pins TIOC4D, TIOC4C, TIOC3D, TIOC4B, TIOC4A, and TIOC3B. These pins do not output correctly if the TOER bits have not been set.
Page 238: Timer Output Control Register 1 (Tocr1)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Value Bit Name Description OE3B Master Enable TIOC3B This bit enables/disables the TIOC3B pin MTU2 output. 0: MTU2 output is disabled (inactive level)* 1: MTU2 output is enabled Note: * The inactive level is determined by the settings in timer output control registers 1 and 2 (TOCR1 and TOCR2).
Page 239 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Bit Name Description Value TOCL R/(W)* TOC Register Write Protection* This bit selects the enable/disable of write access to the TOCS, OLSN, and OLSP bits in TOCR1. 0: Write access to the TOCS, OLSN, and OLSP bits is enabled 1: Write access to the TOCS, OLSN, and OLSP bits is disabled...
Page 240 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.31 Output Level Select Function Bit 0 Function Compare Match Output OLSP Initial Output Active Level Up Count Down Count High level Low level Low level High level Low level High level High level Low level Figure 9.2 shows an example of complementary PWM mode output (1 phase) when OLSN = 1...
Page 241: Timer Output Control Register 2 (Tocr2)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.20 Timer Output Control Register 2 (TOCR2) TOCR2 is an 8-bit readable/writable register that controls output level inversion of PWM output in complementary PWM mode and reset-synchronized PWM mode. Bit: BF[1:0] OLS3N OLS3P OLS2N OLS2P OLS1N OLS1P Initial value: R/W: Initial...
Page 242 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Initial value Bit Name Description OLS1P Output Level Select 1P* This bit selects the output level on TIOC3B in reset- synchronized PWM mode/complementary PWM mode. See table 9.38. Note: * Setting the TOCS bit in TOCR1 to 1 makes this bit setting valid. Table 9.32 Setting of Bits BF1 and BF0 Bit 7 Bit 6...
Page 243 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.34 TIOC4B Output Level Select Function Bit 4 Function Compare Match Output OLS3P Initial Output Active Level Up Count Down Count High level Low level Low level High level Low level High level High level Low level...
Page 244: Timer Output Level Buffer Register (Tolbr)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.38 TIOC3B Output Level Select Function Bit 0 Function Compare Match Output OLS1P Initial Output Active Level Up Count Down Count High level Low level Low level High level Low level High level High level Low level...
Page 245: Timer Gate Control Register (Tgcr)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Figure 9.3 shows an example of the PWM output level setting procedure in buffer operation. Set bit TOCS [1] Set bit TOCS in TOCR1 to 1 to enable the TOCR2 setting. [2] Use bits BF1 and BF0 in TOCR2 to select the TOLBR buffer transfer timing.
Page 246 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Initial value Bit Name Description Reverse Phase Output (N) Control This bit selects whether the level output or the reset- synchronized PWM/complementary PWM output while the reverse pins (TIOC3D, TIOC4C, and TIOC4D) are output.
Page 247: Timer Subcounter (Tcnts)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.39 Output level Select Function Function Bit 2 Bit 1 Bit 0 TIOC3B TIOC4A TIOC4B TIOC3D TIOC4C TIOC4D U Phase V Phase W Phase U Phase V Phase W Phase 9.3.23 Timer Subcounter (TCNTS) TCNTS is a 16-bit read-only counter that is used only in complementary PWM mode.
Page 248: Timer Dead Time Data Register (Tddr)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.24 Timer Dead Time Data Register (TDDR) TDDR is a 16-bit register, used only in complementary PWM mode that specifies the TCNT_3 and TCNT_4 counter offset values. In complementary PWM mode, when the TCNT_3 and TCNT_4 counters are cleared and then restarted, the TDDR register value is loaded into the TCNT_3 counter and the count operation starts.
Page 249: Timer Cycle Buffer Register (Tcbr)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.26 Timer Cycle Buffer Register (TCBR) TCBR is a 16-bit register used only in complementary PWM mode. It functions as a buffer register for the TCDR register. The TCBR register values are transferred to the TCDR register with the transfer timing set in the TMDR register.
Page 250 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Initial value Bit Name Description 2 to 0 4VCOR[2:0] 000 These bits specify the TCIV_4 interrupt skipping count within the range from 0 to 7.* For details, see table 9.41. Note: * When 0 is specified for the interrupt skipping count, no interrupt skipping will be performed.
Page 251: Timer Interrupt Skipping Counter (Titcnt)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.28 Timer Interrupt Skipping Counter (TITCNT) TITCNT is an 8-bit readable/writable counter. The MTU2 has one TITCNT. Bit: 3ACNT[2:0] 4VCNT[2:0] Initial value: R/W: Initial Bit Name Value Description — Reserved This bit is always read as 0. 6 to 4 3ACNT[2:0] TGIA_3 Interrupt Counter...
Page 252: Timer Buffer Transfer Set Register (Tbter)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.29 Timer Buffer Transfer Set Register (TBTER) TBTER is an 8-bit readable/writable register that enables or disables transfer from the buffer registers* used in complementary PWM mode to the temporary registers and specifies whether to link the transfer with interrupt skipping operation.
Page 253 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.42 Setting of Bits BTE1 and BTE0 Bit 1 Bit 0 BTE1 BTE0 Description Enables transfer from the buffer registers to the temporary registers* and does not link the transfer with interrupt skipping operation. Disables transfer from the buffer registers to the temporary registers.
Page 254: Timer Dead Time Enable Register (Tder)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.30 Timer Dead Time Enable Register (TDER) TDER is an 8-bit readable/writable register that controls dead time generation in complementary PWM mode. The MTU2 has one TDER in channel 3. TDER must be modified only while TCNT stops.
Page 255: Timer Waveform Control Register (Twcr)
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.3.31 Timer Waveform Control Register (TWCR) TWCR is an 8-bit readable/writable register that controls the waveform when synchronous counter clearing occurs in TCNT_3 and TCNT_4 in complementary PWM mode and specifies whether to clear the counters at TGRA_3 compare match.
Page 256: Bus Master Interface
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Initial Value Bit Name Description R/(W) Waveform Retain Enable Selects the waveform output when synchronous counter clearing occurs in complementary PWM mode. The output waveform is retained only when synchronous clearing occurs within the Tb interval at the trough in complementary PWM mode.
Page 257: Operation
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation 9.4.1 Basic Functions Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, cycle counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Always select MTU2 external pins set function using the pin function controller (PFC).
Page 258 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 2. Free-Running Count Operation and Periodic Count Operation: Immediately after a reset, the MTU2’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up- count operation as a free-running counter.
Page 259 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Figure 9.6 illustrates periodic counter operation. Counter cleared by TGR TCNT value compare match H'0000 Time CST bit Flag cleared by software Figure 9.6 Periodic Counter Operation Waveform Output by Compare Match: The MTU2 can perform 0, 1, or toggle output from the corresponding output pin using compare match.
Page 260 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 2. Examples of Waveform Output Operation: Figure 9.8 shows an example of 0 output/1 output. In this example, TCNT has been designated as a free-running counter, and settings have been made such that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change.
Page 261 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0 and 1, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source.
Page 262 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 2. Example of Input Capture Operation: Figure 9.11 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, the falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Page 263: Synchronous Operation
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.4.2 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base.
Page 264 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Example of Synchronous Operation in SH7125: Figure 9.13 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Page 265: Buffer Operation
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.4.3 Buffer Operation Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer registers. In channel 0, TGRF can also be used as a buffer register. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register.
Page 266 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 9.15.
Page 267 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Examples of Buffer Operation: 1. When TGR is an output compare register Figure 9.17 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
Page 268 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 H'0F07 H'09FB H'0532 H'0F07 TGRC Figure 9.18 Example of Buffer Operation (2) Selecting Timing for Transfer from Buffer Registers to Timer General Registers in Buffer Operation: The timing for transfer from buffer registers to timer general registers can be selected in PWM mode 1 or 2 for channel 0 or in PWM mode 1 for channels 3 and 4 by setting the buffer operation transfer mode registers (TBTM_0, TBTM_3, and TBTM_4).
Page 269: Cascaded Operation
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT_0 value TGRB_0 H'0520 H'0450 H'0200 TGRA_0 H'0000 Time H'0200 H'0450 H'0520 TGRC_0 Transfer H'0200 H'0450 H'0520 TGRA_0 TIOCA Figure 9.19 Example of Buffer Operation When TCNT_0 Clearing is Selected for TGRC_0 to TGRA_0 Transfer Timing 9.4.4 Cascaded Operation...
Page 270 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.45 shows the TICCR setting and input capture input pins. Table 9.45 TICCR Setting and Input Capture Input Pins Target Input Capture TICCR Setting Input Capture Input Pins Input capture from TCNT_1 to I2AE bit = 0 (initial value) TIOC1A TGRA_1...
Page 271 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TCLKC TCLKD FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF TCNT_2 0000 0001 0000 TCNT_1 Figure 9.21 Cascaded Operation Example (a) Cascaded Operation Example (b) in SH7125: Figure 9.22 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE bit in TICCR has been set to 1 to include the TIOC2A pin in the TGRA_1 input capture conditions.
Page 272 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Cascaded Operation Example (c) in SH7125: Figure 9.23 illustrates the operation when TCNT_1 and TCNT_2 have been cascaded and the I2AE and I1AE bits in TICCR have been set to 1 to include the TIOC2A and TIOC1A pins in the TGRA_1 and TGRA_2 input capture conditions, respectively.
Page 273 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT_0 value Compare match between TCNT_0 and TGRA_0 TGRA_0 Time H'0000 TCNT_2 value H'FFFF H'D000 H'0000 Time H'0512 H'0513 TCNT_1 TIOC1A TIOC2A TGRA_1 H'0513 TGRA_2 H'D000 Figure 9.24 Cascaded Operation Example (d) Rev.
Page 274: Pwm Modes
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.4.5 PWM Modes In PWM mode, PWM waveforms are output from the output pins. The output level can be selected as 0, 1, or toggle output in response to a compare match of each TGR. TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty.
Page 275 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.46 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2 TGRA_0 TIOC0A TIOC0A TGRB_0 TIOC0B TGRC_0 TIOC0C TIOC0C TGRD_0 TIOC0D TGRA_1 TIOC1A* TIOC1A* TGRB_1 TIOC1B* TGRA_2 TIOC2A*...
Page 276 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Example of PWM Mode Setting Procedure: Figure 9.25 shows an example of the PWM mode setting procedure. [1] Select the counter clock with bits TPSC2 to PWM mode TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR.
Page 277 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Figure 9.27 shows an example of PWM mode 2 operation in the SH7125. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase PWM waveform.
Page 278 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Figure 9.28 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value...
Page 279: Phase Counting Mode
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.4.6 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC0 to TPSC2 and bits CKEG0 and CKEG1 in TCR.
Page 280 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. 1.
Page 281 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 2. Phase counting mode 2 Figure 9.31 shows an example of phase counting mode 2 operation, and table 9.49 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Up-count...
Page 282 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 3. Phase counting mode 3 Figure 9.32 shows an example of phase counting mode 3 operation, and table 9.50 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count...
Page 283 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 4. Phase counting mode 4 Figure 9.33 shows an example of phase counting mode 4 operation, and table 9.51 summarizes the TCNT up/down-count conditions. TCLKA (channel 1) TCLKC (channel 2) TCLKB (channel 1) TCLKD (channel 2) TCNT value Down-count...
Page 284 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Phase Counting Mode Application Example: Figure 9.34 shows an example in which channel 1 is in phase counting mode, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect position or speed.
Page 285 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Channel 1 Edge TCLKA TCNT_1 detection TCLKB circuit TGRA_1 (speed period capture) TGRB_1 (position period capture) TCNT_0 TGRA_0 (speed control period) TGRC_0 (position control period) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 Figure 9.34 Phase Counting Mode Application Example Rev.
Page 286: Reset-Synchronized Pwm Mode
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.4.7 Reset-Synchronized PWM Mode In the reset-synchronized PWM mode, three-phase output of positive and negative PWM waveforms that share a common wave transition point can be obtained by combining channels 3 and 4. When set for reset-synchronized PWM mode, the TIOC3B, TIOC3D, TIOC4A, TIOC4C, TIOC4B, and TIOC4D pins function as PWM output pins and TCNT_3 functions as an upcounter.
Page 287 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Procedure for Selecting the Reset-Synchronized PWM Mode: Figure 9.35 shows an example of procedure for selecting the reset synchronized PWM mode. [1] Clear the CST3 and CST4 bits in the TSTR Reset-synchronized to 0 to halt the counting of TCNT.
Page 288 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Reset-Synchronized PWM Mode Operation: Figure 9.36 shows an example of operation in the reset-synchronized PWM mode. TCNT_3 and TCNT_4 operate as upcounters. The counter is cleared when a TCNT_3 and TGRA_3 compare-match occurs, and then begins incrementing from H'0000.
Page 289: Complementary Pwm Mode
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.4.8 Complementary PWM Mode In the complementary PWM mode, three-phase output of non-overlapping positive and negative PWM waveforms can be obtained by combining channels 3 and 4. PWM waveforms without non- overlapping interval is also available. In complementary PWM mode, TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D pins function as PWM output pins, the TIOC3A pin can be set for toggle output synchronized with the PWM period.
Page 290 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.55 Register Settings for Complementary PWM Mode Channel Counter/Register Description Read/Write from CPU TCNT_3 Start of up-count from value set Maskable by TRWER in dead time register setting* TGRA_3 Set TCNT_3 upper limit value Maskable by TRWER (1/2 carrier cycle + dead time) setting*...
Page 291 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TGRC_3 TCBR TDDR TGRA_3 TCDR PWM cycle Comparator Match output signal PWM output 1 PWM output 2 TCNT_3 TCNTS TCNT_4 PWM output 3 PWM output 4 PWM output 5 Comparator PWM output 6 Match External cutoff signal...
Page 292 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Example of Complementary PWM Mode Setting Procedure: An example of the complementary PWM mode setting procedure is shown in figure 9.38. [1] Clear bits CST3 and CST4 in the timer start register (TSTR) to 0, and halt timer counter (TCNT) operation.
Page 293 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Outline of Complementary PWM Mode Operation: In complementary PWM mode, 6-phase PWM output is possible. Figure 9.39 illustrates counter operation in complementary PWM mode, and figure 9.40 shows an example of complementary PWM mode operation.
Page 294 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 2. Register Operation In complementary PWM mode, nine registers are used, comprising compare registers, buffer registers, and temporary registers. Figure 9.40 shows an example of complementary PWM mode operation. The registers which are constantly compared with the counters to perform PWM output are TGRB_3, TGRA_4, and TGRB_4.
Page 295 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Transfer from temporary Transfer from temporary register to compare register register to compare register TGRA_3 TCNTS TCDR TCNT_3 TGRA_4 TCNT_4 TGRC_4 TDDR H'0000 Buffer register H'6400 H'0080 TGRC_4 Temporary register H'6400 H'0080 TEMP2 Compare register H'6400...
Page 296 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 3. Initialization In complementary PWM mode, there are six registers that must be initialized. In addition, there is a register that specifies whether to generate dead time (it should be used only when dead time generation should be disabled).
Page 297 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 4. PWM Output Level Setting In complementary PWM mode, the PWM pulse output level is set with bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1P to OLS3P and OLS1N to OLS3N in timer output control register 2 (TOCR2).
Page 298 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Transfer from temporary register Transfer from temporary register to compare register to compare register TGRA_3=TCDR+1 TCNTS TCDR TCNT_3 TCNT_4 TGRA_4 TGRC_4 TDDR=1 H'0000 Buffer register TGRC_4 Data1 Data2 Data1 Data2 Temporary register TEMP2 Compare register TGRA_4 Data1 Data2...
Page 299 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 7. PWM Cycle Setting In complementary PWM mode, the PWM pulse cycle is set in two registers—TGRA_3, in which the TCNT_3 upper limit value is set, and TCDR, in which the TCNT_4 upper limit value is set.
Page 300 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 8. Register Data Updating In complementary PWM mode, the buffer register is used to update the data in a compare register. The update data can be written to the buffer register at any time. There are five PWM duty and carrier cycle registers that have buffer registers and can be updated during operation.
Page 301 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Figure 9.43 Example of Data Update in Complementary PWM Mode Rev. 3.00 Sep. 27, 2007 Page 281 of 758 REJ09B0243-0300...
Page 302 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9. Initial Output in Complementary PWM Mode In complementary PWM mode, the initial output is determined by the setting of bits OLSN and OLSP in timer output control register 1 (TOCR1) or bits OLS1N to OLS3N and OLS1P to OLS3P in timer output control register 2 (TOCR2).
Page 303 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Timer output control register settings OLSN bit: 0 (initial output: high; active level: low) OLSP bit: 0 (initial output: high; active level: low) TCNT_3 and TCNT_4 values TCNT_3 TCNT_4 TDDR TGRA_4 Time Initial output Positive phase Active level...
Page 304 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 10. Complementary PWM Mode PWM Output Generation Method In complementary PWM mode, 3-phase output is performed of PWM waveforms with a non- overlap time between the positive and negative phases. This non-overlap time is called the dead time.
Page 305 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) T2 period T1 period T1 period TGRA_3 TCDR TDDR H'0000 Positive phase Negative phase Figure 9.46 Example of Complementary PWM Mode Waveform Output (1) T2 period T1 period T1 period TGRA_3 TCDR TDDR H'0000 Positive phase...
Page 306 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) T1 period T2 period T1 period TGRA_3 TCDR TDDR H'0000 Positive phase Negative phase Figure 9.48 Example of Complementary PWM Mode Waveform Output (3) T1 period T2 period T1 period TGRA_3 TCDR TDDR H'0000 Positive phase...
Page 307 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) T1 period T2 period T1 period TGRA_3 TCDR TDDR H'0000 Positive phase Negative phase Figure 9.50 Example of Complementary PWM Mode 0% and 100% Waveform Output (2) T1 period T2 period T1 period TGRA_3 TCDR TDDR...
Page 308 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) T1 period T2 period T1 period TGRA_3 TCDR TDDR H'0000 c b' d a' Positive phase Negative phase Figure 9.52 Example of Complementary PWM Mode 0% and 100% Waveform Output (4) T1 period T2 period T1 period TGRA_3...
Page 309 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 11. Complementary PWM Mode 0% and 100% Duty Output In complementary PWM mode, 0% and 100% duty cycles can be output as required. Figures 9.49 to 9.53 show output examples. 100% duty output is performed when the data register value is set to H'0000. The waveform in this case has a positive phase with a 100% on-state.
Page 310 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 13. Counter Clearing by Another Channel In complementary PWM mode, by setting a mode for synchronization with another channel by means of the timer synchronous register (TSYR), and selecting synchronous clearing with bits CCLR2 to CCLR0 in the timer control register (TCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by another channel.
Page 311 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 14. Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode Setting the WRE bit in TWCR to 1 suppresses initial output when synchronous counter clearing occurs in the Tb interval at the trough in complementary PWM mode and controls abrupt change in duty cycle at synchronous counter clearing.
Page 312 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2)  Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing in Complementary PWM Mode An example of the procedure for setting output waveform control at synchronous counter clearing in complementary PWM mode is shown in figure 9.57. Output waveform control at [1] Clear bits CST3 and CST4 in the timer synchronous counter clearing...
Page 313 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Synchronous clearing Bit WRE = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 9.58 Example of Synchronous Clearing in Dead Time during Up-Counting (Timing (3) in Figure 9.56;...
Page 314 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Synchronous clearing Bit WRE = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 9.59 Example of Synchronous Clearing in Interval Tb at Crest (Timing (6) in Figure 9.56;...
Page 315 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Synchronous clearing Bit WRE = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Negative phase Output waveform is active-low. Figure 9.60 Example of Synchronous Clearing in Dead Time during Down-Counting (Timing (8) in Figure 9.56;...
Page 316 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Synchronous clearing Bit WRE = 1 TGRA_3 TCDR TGRB_3 TCNT_3 (MTU2) TCNT_4 (MTU2) TDDR H'0000 Positive phase Initial value output is suppressed. Negative phase Output waveform is active-low. Figure 9.61 Example of Synchronous Clearing in Interval Tb at Trough (Timing (11) in Figure 9.56;...
Page 317 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 15. Counter Clearing by TGRA_3 Compare Match In complementary PWM mode, by setting the CCE bit in the timer waveform control register (TWCR), it is possible to have TCNT_3, TCNT_4, and TCNTS cleared by TGRA_3 compare match.
Page 318 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 16. Example of AC Synchronous Motor (Brushless DC Motor) Drive Waveform Output In complementary PWM mode, a brushless DC motor can easily be controlled using the timer gate control register (TGCR). Figures 9.63 to 9.66 show examples of brushless DC motor drive waveforms created using TGCR.
Page 319 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) External input TIOC0A pin TIOC0B pin TIOC0C pin 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 0, output active level = high Figure 9.64 Example of Output Phase Switching by External Input (2) TGCR UF bit...
Page 320 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TGCR UF bit VF bit WF bit 6-phase output TIOC3B pin TIOC3D pin TIOC4A pin TIOC4C pin TIOC4B pin TIOC4D pin When BDC = 1, N = 1, P = 1, FB = 1, output active level = high Figure 9.66 Example of Output Phase Switching by Means of UF, VF, WF Bit Settings (2) 17.
Page 321 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Interrupt Skipping in Complementary PWM Mode: Interrupts TGIA_3 (at the crest) and TCIV_4 (at the trough) in channels 3 and 4 can be skipped up to seven times by making settings in the timer interrupt skipping set register (TITCR). Transfers from a buffer register to a temporary register or a compare register can be skipped in coordination with interrupt skipping by making settings in the timer buffer transfer register (TBTER).
Page 322 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT_3 TCNT_4 Period during which Period during which Period during which Period during which changing skipping count changing skipping count changing skipping count changing skipping count can be performed can be performed can be performed can be performed Figure 9.68 Periods during which Interrupt Skipping Count can be Changed...
Page 323 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 3. Buffer Transfer Control Linked with Interrupt Skipping In complementary PWM mode, whether to transfer data from a buffer register to a temporary register and whether to link the transfer with interrupt skipping can be specified with the BTE1 and BTE0 bits in the timer buffer transfer set register (TBTER).
Page 324 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT_3 TCNT_4 data1 Bit BTE0 in TBTER Bit BTE1 in TBTER Buffer register Data1 Data2 Temporary register Data* Data2 General register Data* Data2 Buffer transfer is suppressed [Legend] (1) No data is transferred from the buffer register to the temporary register in the buffer transfer-disabled period (bits BTE1 and BTE0 in TBTER are set to 0 and 1, respectively).
Page 325 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) (1) When rewriting a buffer register within a carrier cycle after TGIA_3 interrupt occurred. TGIA_3 interrupt occurred TGIA_3 interrupt occurred TCNT_3 TCNT_4 Buffer register rewriting timing Buffer register rewriting timing Buffer transfer-enabled period TITCR[6:4] TITCNT[6:4] Buffer register...
Page 326 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Skipping counter 3ACNT Skipping counter 4VCNT Buffer transfer-enabled period (T3AEN is set to 1) Buffer transfer-enabled period (T4VEN is set to 1) Buffer transfer-enabled period (T3AEN and T4VEN are set to 1) Note: * The skipping count is set to three.
Page 327 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Complementary PWM Mode Output Protection Function: Complementary PWM mode output has the following protection functions. 1. Register and counter miswrite prevention function With the exception of the buffer registers, which can be rewritten at any time, access by the CPU can be enabled or disabled for the mode registers, control registers, compare registers, and counters used in complementary PWM mode by means of the RWE bit in the timer read/write enable register (TRWER).
Page 328: A/D Converter Start Request Delaying Function
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.4.9 A/D Converter Start Request Delaying Function A/D converter start requests can be issued in channel 4 by making settings in the timer A/D converter start request control register (TADCR), timer A/D converter start request cycle set registers (TADCORA_4 and TADCORB_4), and timer A/D converter start request cycle set buffer registers (TADCOBRA_4 and TADCOBRB_4).
Page 329 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 2. Basic Operation Example of A/D Converter Start Request Delaying Function Figure 9.74 shows a basic example of A/D converter request signal (TRG4AN) operation when the trough of TCNT_4 is specified for the buffer transfer timing and an A/D converter start request signal is output during TCNT_4 down-counting.
Page 330 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Note: This function must be used in combination with interrupt skipping. When interrupt skipping is disabled (the T3AEN and T4VEN bits in the timer interrupt skipping set register (TITCR) are cleared to 0 or the skipping count set bits (3ACOR and 4VCOR) in TITCR are cleared to 0), make sure that A/D converter start requests are not linked with interrupt skipping (clear the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in the timer A/D converter start request control register (TADCR) to 0).
Page 331 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT_4 TADCORA_4 TGIA_3 interrupt skipping counter TCIV_4 interrupt skipping counter TGIA_3 A/D request-enabled period TCIV_4 A/D request-enabled period A/D converter start request (TRG4AN) When linked with TGIA_3 and TCIV_4 interrupt skipping When linked with TGIA_3 interrupt skipping When linked with TCIV_4 interrupt skipping...
Page 332: External Pulse Width Measurement
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.4.10 External Pulse Width Measurement The pulse widths of up to three external input lines can be measured in channel 5. Example of External Pulse Width Measurement Setting Procedure: [1] Use bits TPSC1 and TPSC0 in TCR to select the External pulse width counter clock.
Page 333: Dead Time Compensation
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.4.11 Dead Time Compensation By measuring the delay of the output waveform and reflecting it to duty, the external pulse width measurement function can be used as the dead time compensation function while the complementary PWM is in operation.
Page 334 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Example of Dead Time Compensation Setting Procedure: Figure 9.80 shows an example of dead time compensation setting procedure by using three counters in channel 5. [1] Place channels 3 and 4 in complementary PWM mode. For details, refer to section 9.4.8, Complementary PWM Mode.
Page 335: Tcnt Capture At Crest And/Or Trough In Complementary Pwm Operation
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.4.12 TCNT Capture at Crest and/or Trough in Complementary PWM Operation The TCNT value is captured in TGR at either the crest or trough or at both the crest and trough during complementary PWM operation. The timing for capturing in TGR can be selected by TIOR.
Page 336: Interrupt Sources
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Interrupt Sources 9.5.1 Interrupt Sources and Priorities There are three kinds of MTU2 interrupt source; TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing the generation of interrupt request signals to be enabled or disabled individually.
Page 337 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.57 MTU2 Interrupts Channel Name Interrupt Source Interrupt Flag Priority TGIA_0 TGRA_0 input capture/compare match TGFA_0 High TGIB_0 TGRB_0 input capture/compare match TGFB_0 TGIC_0 TGRC_0 input capture/compare match TGFC_0 TGID_0 TGRD_0 input capture/compare match TGFD_0 TCIV_0 TCNT_0 overflow...
Page 338 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel.
Page 339: A/D Converter Activation
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.5.2 A/D Converter Activation The A/D converter can be activated by one of the following three methods in the MTU2. Table 9.58 shows the relationship between interrupt sources and A/D converter start request signals. A/D Converter Activation by TGRA Input Capture/Compare Match or at TCNT_4 Trough in Complementary PWM Mode: The A/D converter can be activated by the occurrence of a TGRA input capture/compare match in each channel.
Page 340 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Table 9.58 Interrupt Sources and A/D Converter Start Request Signals A/D Converter Start Request Signal Target Registers Interrupt Source TGRA_0 and TCNT_0 Input capture/compare match TRGAN TGRA_1 and TCNT_1 TGRA_2 and TCNT_2 TGRA_3 and TCNT_3 TGRA_4 and TCNT_4 TCNT_4...
Page 341: Operation Timing
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation Timing 9.6.1 Input/Output Timing TCNT Count Timing: Figures 9.83 and 9.84 show TCNT count timing in internal clock operation, and figure 9.85 shows TCNT count timing in external clock operation (normal mode), and figure 9.86 shows TCNT count timing in external clock operation (phase counting mode).
Page 342 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) MPφ External Rising edge Falling edge clock TCNT input clock N - 1 N - 1 TCNT Figure 9.86 Count Timing in External Clock Operation (Phase Counting Mode) Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated).
Page 343 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) MPφ TCNT input clock N + 1 TCNT Compare match signal TIOC pin Figure 9.88 Output Compare Output Timing (Complementary PWM Mode/Reset Synchronous PWM Mode) Input Capture Signal Timing: Figure 9.89 shows input capture signal timing. MPφ...
Page 344 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Timing for Counter Clearing by Compare Match/Input Capture: Figures 9.90 and 9.91 show the timing when counter clearing on compare match is specified, and figure 9.92 shows the timing when counter clearing on input capture is specified. MPφ...
Page 345 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) MPφ Input capture signal Counter clear signal H'0000 TCNT Figure 9.92 Counter Clear Timing (Input Capture) Buffer Operation Timing: Figures 9.93 to 9.95 show the timing in buffer operation. MPφ TCNT n + 1 Compare match buffer signal...
Page 346 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) MPφ TCNT H'0000 TCNT clear signal Buffer transfer signal TGRA, TGRB, TGRE TGRC, TGRD, TGRF Figure 9.95 Buffer Transfer Timing (when TCNT Cleared) Buffer Transfer Timing (Complementary PWM Mode): Figures 9.96 to 9.98 show the buffer transfer timing in complementary PWM mode.
Page 347 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) MPφ TCNTS P - x H'0000 TGRD_4 write signal Buffer register Temporary register Figure 9.97 Transfer Timing from Buffer Register to Temporary Register (TCNTS Operating) MPφ TCNTS P - 1 H'0000 Buffer transfer signal Temporary register...
Page 348: Interrupt Signal Timing
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figures 9.99 and 9.100 show the timing for setting of the TGF flag in TSR on compare match, and TGI interrupt request signal timing. MPφ...
Page 349 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TGF Flag Setting Timing in Case of Input Capture: Figures 9.101 and 9.102 show the timing for setting of the TGF flag in TSR on input capture, and TGI interrupt request signal timing. MPφ, Pφ...
Page 350 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TCFV Flag/TCFU Flag Setting Timing: Figure 9.103 shows the timing for setting of the TCFV flag in TSR on overflow, and TCIV interrupt request signal timing. Figure 9.104 shows the timing for setting of the TCFU flag in TSR on underflow, and TCIU interrupt request signal timing.
Page 351 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. Figures 9.105 and 9.106 show the timing for status flag clearing by the CPU. TSR write cycle MPφ, Pφ...
Page 352: Usage Notes
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Usage Notes 9.7.1 Module Standby Mode Setting MTU2 operation can be disabled or enabled using the standby control register. The initial setting is for MTU2 operation to be halted. Register access is enabled by clearing module standby mode. For details, refer to section 19, Power-Down Modes.
Page 353: Caution On Period Setting
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.3 Caution on Period Setting When counter clearing on compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: •...
Page 354: Contention Between Tcnt Write And Increment Operations
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.5 Contention between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 9.109 shows the timing in this case. TCNT write cycle MPφ...
Page 355: Contention Between Tgr Write And Compare Match
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.6 Contention between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed and the compare match signal is also generated. Figure 9.110 shows the timing in this case.
Page 356: Contention Between Buffer Register Write And Compare Match
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.7 Contention between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data before write. Figure 9.111 shows the timing in this case.
Page 357: Contention Between Buffer Register Write And Tcnt Clear
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.8 Contention between Buffer Register Write and TCNT Clear When the buffer transfer timing is set at the TCNT clear by the buffer transfer mode register (TBTM), if TCNT clear occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR by the buffer operation is the data before write.
Page 358: Contention Between Tgr Read And Input Capture
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.9 Contention between TGR Read and Input Capture If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data in the buffer before input capture transfer for channels 0 to 4, and the data after input capture transfer for channel 5.
Page 359: Contention Between Tgr Write And Input Capture
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.10 Contention between TGR Write and Input Capture If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed for channels 0 to 4. For channel 5, write to TGR is performed and the input capture signal is generated.
Page 360: Contention Between Buffer Register Write And Input Capture
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.11 Contention between Buffer Register Write and Input Capture If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 9.117 shows the timing in this case.
Page 361 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) TCNT write cycle MPφ Address TCNT_2 address Write signal TCNT_2 H'FFFE H'FFFF N + 1 TCNT_2 write data TGRA_2 to H'FFFF TGRB_2 Ch2 compare- match signal A/B Disabled TCNT_1 input clock TCNT_1 TGRA_1 Ch1 compare- match signal A...
Page 362: Counter Value During Complementary Pwm Mode Stop
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.13 Counter Value during Complementary PWM Mode Stop When counting operation is suspended with TCNT_3 and TCNT_4 in complementary PWM mode, TCNT_3 has the timer dead time register (TDDR) value, and TCNT_4 is held at H'0000. When restarting complementary PWM mode, counting begins automatically from the initialized state.
Page 363: Reset Sync Pwm Mode Buffer Operation And Compare Match Flag
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag When setting buffer operation for reset sync PWM mode, set the BFA and BFB bits in TMDR_4 to 0. The TIOC4C pin will be unable to produce its waveform output if the BFA bit in TMDR_4 is set to 1.
Page 364: Overflow Flags In Reset Synchronous Pwm Mode
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.16 Overflow Flags in Reset Synchronous PWM Mode When set to reset synchronous PWM mode, TCNT_3 and TCNT_4 start counting when the CST3 bit in TSTR is set to 1. At this point, TCNT_4's count clock source and count edge obey the TCR_3 setting.
Page 365: Contention Between Overflow/Underflow And Counter Clearing
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.17 Contention between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 9.122 shows the operation timing when a TGR compare match is specified as the clearing source, and when H'FFFF is set in TGR.
Page 366: Contention Between Tcnt Write And Overflow/Underflow
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.18 Contention between TCNT Write and Overflow/Underflow If there is an up-count or down-count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set.
Page 367: Output Level In Complementary Pwm Mode And Reset-Synchronized Pwm Mode
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode When channels 3 and 4 are in complementary PWM mode or reset-synchronized PWM mode, the PWM waveform output level is set with the OLSP and OLSN bits in the timer output control register (TOCR).
Page 368: Mtu2 Output Pin Initialization
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) MTU2 Output Pin Initialization 9.8.1 Operating Modes The MTU2 has the following six operating modes. Waveform output is possible in all of these modes. • Normal mode (channels 0 to 4) • PWM mode 1 (channels 0 to 4) •...
Page 369: Operation In Case Of Re-Setting Due To Error During Operation, Etc
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.8.3 Operation in Case of Re-Setting Due to Error During Operation, etc. If an error occurs during MTU2 operation, MTU2 output should be cut by the system. Cutoff is performed by switching the pin output to port output with the PFC and outputting the inverse of the active level.
Page 370: Overview Of Initialization Procedures And Mode Transitions In Case Of Error During Operation, Etc
Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) 9.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, etc. • When making a transition to a mode (Normal, PWM1, PWM2, PCM) in which the pin output level is selected by the timer I/O control register (TIOR) setting, initialize the pins by means of a TIOR setting.
Page 371 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Pin initialization procedures are described below for the numbered combinations in table 9.59. The active level is assumed to be low. Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Normal Mode: Figure 9.124 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in normal mode after re-setting.
Page 372 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 9.125 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 1 after re-setting. RESET TMDR TOER...
Page 373 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 9.126 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in PWM mode 2 after re-setting. RESET TMDR TOER...
Page 374 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Phase Counting Mode: Figure 9.127 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in phase counting mode after re-setting. RESET TMDR TOER...
Page 375 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 9.128 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in complementary PWM mode after re- setting.
Page 376 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Normal Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode: Figure 9.129 shows an explanatory diagram of the case where an error occurs in normal mode and operation is restarted in reset-synchronized PWM mode after re-setting.
Page 377 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Normal Mode: Figure 9.130 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in normal mode after re-setting. RESET TMDR TOER...
Page 378 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 1: Figure 9.131 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 1 after re-setting. RESET TMDR TOER...
Page 379 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in PWM Mode 2: Figure 9.132 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in PWM mode 2 after re-setting. RESET TMDR TOER...
Page 380 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Phase Counting Mode: Figure 9.133 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in phase counting mode after re-setting. RESET TMDR TOER...
Page 381 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Complementary PWM Mode: Figure 9.134 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in complementary PWM mode after re- setting.
Page 382 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 1 Operation, and Operation is Restarted in Reset-Synchronized PWM Mode: Figure 9.135 shows an explanatory diagram of the case where an error occurs in PWM mode 1 and operation is restarted in reset-synchronized PWM mode after re-setting.
Page 383 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Normal Mode: Figure 9.136 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in normal mode after re-setting. RESET TMDR TIOR...
Page 384 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 1: Figure 9.137 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 1 after re-setting. RESET TMDR TIOR...
Page 385 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in PWM Mode 2: Figure 9.138 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in PWM mode 2 after re-setting. RESET TMDR TIOR...
Page 386 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is Restarted in Phase Counting Mode: Figure 9.139 shows an explanatory diagram of the case where an error occurs in PWM mode 2 and operation is restarted in phase counting mode after re-setting. RESET TMDR TIOR...
Page 387 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Normal Mode: Figure 9.140 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in normal mode after re-setting. RESET TMDR TIOR...
Page 388 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 9.141 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 1 after re-setting. RESET TMDR TIOR...
Page 389 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in PWM Mode 2: Figure 9.142 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in PWM mode 2 after re-setting. RESET TMDR TIOR...
Page 390 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Phase Counting Mode Operation, and Operation is Restarted in Phase Counting Mode: Figure 9.143 shows an explanatory diagram of the case where an error occurs in phase counting mode and operation is restarted in phase counting mode after re-setting.
Page 391 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Normal Mode: Figure 9.144 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in normal mode after re-setting.
Page 392 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 9.145 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in PWM mode 1 after re-setting.
Page 393 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 9.146 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using the cycle and duty settings at the time the counter was stopped).
Page 394 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 9.147 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in complementary PWM mode after re-setting (when operation is restarted using completely new cycle and duty settings).
Page 395 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Complementary PWM Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode: Figure 9.148 shows an explanatory diagram of the case where an error occurs in complementary PWM mode and operation is restarted in reset-synchronized PWM mode after re-setting.
Page 396 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Normal Mode: Figure 9.149 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in normal mode after re-setting.
Page 397 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in PWM Mode 1: Figure 9.150 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in PWM mode 1 after re-setting.
Page 398 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Complementary PWM Mode: Figure 9.151 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in complementary PWM mode after re-setting.
Page 399 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Operation when Error Occurs during Reset-Synchronized PWM Mode Operation, and Operation is Restarted in Reset-Synchronized PWM Mode: Figure 9.152 shows an explanatory diagram of the case where an error occurs in reset-synchronized PWM mode and operation is restarted in reset-synchronized PWM mode after re-setting.
Page 400 Section 9 Multi-Function Timer Pulse Unit 2 (MTU2) Rev. 3.00 Sep. 27, 2007 Page 380 of 758 REJ09B0243-0300...
Page 401: Section 10 Port Output Enable (Poe)
Section 10 Port Output Enable (POE) Section 10 Port Output Enable (POE) The port output enable (POE) can be used to place the high-current pins (pins multiplexed with TIOC3B, TIOC3D, TIOC4A, TIOC4B, TIOC4C, and TIOC4D in the MTU2) and the pins for channel 0 of the MTU2 (pins multiplexed with TIOC0A, TIOC0B, TIOC0C, and TIOC0D) in high-impedance state, depending on the change on POE0, POE1, POE3*, and POE8 input pins and the output status of the high-current pins, or by modifying register settings.
Page 402 Section 10 Port Output Enable (POE) Figure 10.1 shows a block diagram of the POE. POECR1, POECR2 TIOC3B Output level comparison circuit TIOC3D TIOC4A Output level comparison circuit TIOC4C High-impedance TIOC4B Output level comparison circuit request signal for MTU2 TIOC4D high-current pins High-impedance Input level detection circuit...
Page 403: Input/Output Pins
Section 10 Port Output Enable (POE) 10.2 Input/Output Pins Table 10.1 Pin Configuration Name Abbreviation Description POE0, POE1, Port output enable input pins Input Input request signals to place high- POE3* 0, 1, 3 current pins for MTU2 in high- impedance state* Port output enable input pin 8 POE8 Input...
Page 404: Register Descriptions
Section 10 Port Output Enable (POE) 10.3 Register Descriptions The POE has the following registers. For details on register addresses and register states during each processing, refer to section 20, List of Registers. Table 10.3 Register Configuration Abbrevia- Register Name tion Initial Value Address...
Page 405: Input Level Control/Status Register 1 (Icsr1)
Section 10 Port Output Enable (POE) 10.3.1 Input Level Control/Status Register 1 (ICSR1) ICSR1 is a 16-bit readable/writable register that selects the POE0, POE1, and POE3 pin input modes, controls the enable/disable of interrupts, and indicates status. Bit: POE3F POE1F POE0F PIE1 POE3M[1:0] POE1M[1:0]...
Page 406 Section 10 Port Output Enable (POE) Initial value Bit Name Description POE1F R/(W)* POE1 Flag This flag indicates that a high impedance request has been input to the POE1 pin. [Clearing conditions] • By writing 0 to POE1F after reading POE1F = 1 (when the falling edge is selected by bits 3 and 2 in ICSR1) •...
Page 407 Section 10 Port Output Enable (POE) Initial value Bit Name Description PIE1 Port Interrupt Enable 1 This bit enables/disables interrupt requests when any one of the POE0F to POE3F bits of the ICSR1 is set to 1. 0: Interrupt requests disabled 1: Interrupt requests enabled 7, 6 POE3M[1:0]...
Page 408: Output Level Control/Status Register 1 (Ocsr1)
Section 10 Port Output Enable (POE) Initial value Bit Name Description 1, 0 POE0M[1:0] R/W* POE0 mode 1, 0 These bits select the input mode of the POE0 pin. 00: Accept request on falling edge of POE0 input 01: Accept request when POE0 input has been sampled for 16 Pφ/8 clock pulses and all are low level.
Page 409: Input Level Control/Status Register 3 (Icsr3)
Section 10 Port Output Enable (POE) Initial value Bit Name Description 14 to 10  All 0 Reserved These bits are always read as 0. The write value should always be 0. OCE1 R/W* Output Short High-Impedance Enable 1 This bit specifies whether to place the pins in high- impedance state when the OSF1 bit in OCSR1 is set to 1.
Page 410 Section 10 Port Output Enable (POE) Initial value Bit Name Description 15 to 13 — All 0 Reserved These bits are always read as 0. The write value should always be 0. POE8F R/(W)* POE8 Flag This flag indicates that a high impedance request has been input to the POE8 pin.
Page 411: Software Port Output Enable Register (Spoer)
Section 10 Port Output Enable (POE) Initial value Bit Name Description  7 to 2 All 0 Reserved These bits are always read as 0. The write value should always be 0. 1, 0 POE8M[1:0] 00 R/W* POE8 mode 1 and 0 These bits select the input mode of the POE8 pin.
Page 412 Section 10 Port Output Enable (POE) Initial value Bit Name Description MTU2CH0HIZ MTU2 Channel 0 Output High-Impedance This bit specifies whether to place the pins for channel 0 in the MTU2 in high-impedance state. 0: Does not place the pins in high-impedance state [Clearing conditions] •...
Page 413: Port Output Enable Control Register 1 (Poecr1)
Section 10 Port Output Enable (POE) 10.3.5 Port Output Enable Control Register 1 (POECR1) POECR1 is an 8-bit readable/writable register that controls high-impedance state of the pins. Bit: MTU2 MTU2 MTU2 MTU2 PE3ZE PE2ZE PE1ZE PE0ZE Initial value: R/W: R/W* R/W* R/W* R/W* Note: Can be modified only once after a power-on reset.
Page 414: Port Output Enable Control Register 2 (Poecr2)
Section 10 Port Output Enable (POE) Initial value Bit Name Description MTU2PE0ZE R/W* MTU2 PE0 High-Impedance Enable This bit specifies whether to place the PE0/TIOC1A pin for channel 0 in the MTU2 in high-impedance state when either POE8F or MTU2CH0HIZ bit is set to 1.
Page 415 Section 10 Port Output Enable (POE) Initial value Bit Name Description MTU2P2CZE R/W* MTU2 Port 2 Output Comparison/High-Impedance Enable This bit specifies whether to compare output levels for the MTU2 high-current PE12/TIOC4A and PE14/TIOC4C pins and to place them in high- impedance state when the OSF1 bit is set to 1 while the OEC1 bit is 1 or when any one of the POE0F, POE1F, POE3F, and MTU2CH34HIZ bits is set to 1.
Page 416: Operation
Section 10 Port Output Enable (POE) 10.4 Operation Table 10.4 shows the target pins for high-impedance control and conditions to place the pins in high-impedance state. Table 10.4 Target Pins and Conditions for High-Impedance Control Pins Conditions Detailed Conditions MTU2P1CZE • MTU2 high-current pins Input level detection, (PE9/TIOC3B and...
Page 417 Section 10 Port Output Enable (POE) Pφ Pφ rising edge POE input Falling edge detection PE9/TIOC3B High-impedance state* Note: * The other high-current pins also enter the high-impedance state in the similar timing. Figure 10.2 Falling Edge Detection Low-Level Detection Figure 10.3 shows the low-level detection operation.
Page 418: Output-Level Compare Operation
Section 10 Port Output Enable (POE) 10.4.2 Output-Level Compare Operation Figure 10.4 shows an example of the output-level compare operation for the combination of TIOC3B and TIOC3D. The operation is the same for the other pin combinations. Pφ Low level overlapping detected PE9/ TIOC3B PE11/...
Page 419: Interrupts
Section 10 Port Output Enable (POE) 10.5 Interrupts The POE issues a request to generate an interrupt when the specified condition is satisfied during input level detection or output level comparison. Table 10.5 shows the interrupt sources and their conditions. Table 10.5 Interrupt Sources and Conditions Name Interrupt Source...
Page 420: Usage Note
Section 10 Port Output Enable (POE) 10.6 Usage Note 10.6.1 Pin State when a Power-On Reset is Issued from the Watchdog Timer When a power-on reset is issued from the watchdog timer (WDT), initialization of the pin function controller (PFC) sets initial values that select the general input function for the I/O ports. However, when a power-on reset is issued from the WDT while a pin is being handled as high impedance by the port output enable (POE), the pin is placed in the output state for one cycle of the peripheral clock (Pf), after which the function is switched to general input.
Page 421: Section 11 Watchdog Timer (Wdt)
Section 11 Watchdog Timer (WDT) Section 11 Watchdog Timer (WDT) This LSI includes the watchdog timer (WDT). This LSI can be reset by the overflow of the counter when the value of the counter has not been updated because of a system runaway. The watchdog timer (WDT) is a single-channel timer that uses a peripheral clock as an input and counts the clock settling time when clearing software standby mode.
Page 422 Section 11 Watchdog Timer (WDT) Figure 11.1 shows a block diagram of the WDT. Standby Standby Standby mode cancellation control Peripheral clock (Pφ) WDTOVF Reset Divider Internal reset control request Clock selection Clock selector Overflow Interrupt Interrupt Clock request control WTCSR WTCNT Bus interface...
Page 423: Input/Output Pin For Wdt
Section 11 Watchdog Timer (WDT) 11.2 Input/Output Pin for WDT Table 11.1 lists the WDT pin configuration. Table 11.1 WDT Pin Configuration Pin Name Abbreviation I/O Description WDTOVF Watchdog timer Output When an overflow occurs in watchdog timer mode, overflow an internal reset is generated and this pin outputs the low level for one clock cycle specified by the CKS2 to CKS0 bits in WTCSR.
Page 424: Register Descriptions
Section 11 Watchdog Timer (WDT) 11.3 Register Descriptions The WDT has the following two registers. Refer to section 20, List of Registers, for the details of the addresses of these registers and the state of registers in each operating mode. Table 11.2 Register Configuration Abbrevia- Register Name...
Page 425: Watchdog Timer Control/Status Register (Wtcsr)
Section 11 Watchdog Timer (WDT) 11.3.2 Watchdog Timer Control/Status Register (WTCSR) WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the count, bits to select the timer mode, and overflow flags. WTCSR holds its value in an internal reset due to the WDT overflow.
Page 426 Section 11 Watchdog Timer (WDT) Initial Value Bit Name Description RSTS Reset Select Selects the type of reset when the WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. 0: Power-on reset 1: Manual reset WOVF Watchdog Timer Overflow Indicates that the WTCNT has overflowed in watchdog...
Page 427: Notes On Register Access
Section 11 Watchdog Timer (WDT) 11.3.3 Notes on Register Access The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are more difficult to write to than other registers. The procedure for writing to these registers is given below. Writing to WTCNT and WTCSR: These registers must be written by a word transfer instruction.
Page 428: Operation
Section 11 Watchdog Timer (WDT) 11.4 Operation 11.4.1 Canceling Software Standbys The WDT can be used to revoke software standby mode with an NMI interrupt or external interrupt (IRQ). The procedure is described below. (The WDT does not run when resets are used for canceling, so keep the RES pin low until the clock stabilizes.) 1.
Page 429: Using Interval Timer Mode
Section 11 Watchdog Timer (WDT) WTCNT value Overflow occurs H'FF Time H'00 WT/IT = 1 H'00 is written WOVF = 1 H'00 is written TME = 1 to WTCNT to WTCNT WDTOVF is asserted and an internal reset is generated Count starts WDTOVF signal 32 Pφ...
Page 430: Usage Note
Section 11 Watchdog Timer (WDT) 11.5 Usage Note If WTCNT is set to H'FF in interval timer mode, overflow does not occur when WTCNT reaches the immediate H'00, but occurs when WTCNT changes from H'FF to H'00 after 257 cycles of count clock.
Page 431: Section 12 Serial Communication Interface (Sci)
Section 12 Serial Communication Interface (SCI) Section 12 Serial Communication Interface (SCI) This LSI has three independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clock synchronous serial communication. In asynchronous serial communication mode, serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
Page 432 Section 12 Serial Communication Interface (SCI) • Four types of interrupts: There are four interrupt sources, transmit-data-empty, transmit end, receive-data-full, and receive error interrupts, and each interrupt can be requested independently. • Module standby mode can be set Figure 12.1 shows a block diagram of the SCI. Module data bus Internal data bus...
Page 433: Input/Output Pins
Section 12 Serial Communication Interface (SCI) 12.2 Input/Output Pins The SCI has the serial pins summarized in table 12.1. Table 12.1 Pin Configuration Channel Pin Name* Function SCK0 SCI0 clock input/output RXD0 Input SCI0 receive data input TXD0 Output SCI0 transmit data output SCK1* SCI1 clock input/output RXD1...
Page 434: Register Descriptions
Section 12 Serial Communication Interface (SCI) 12.3 Register Descriptions The SCI has the following registers for each channel. For details on register addresses and register states during each processing, see section 20, List of Registers. Table 12.2 Register Configuration Chan- Abbrevia- Access Register Name...
Page 435: Receive Shift Register (Scrsr)
Section 12 Serial Communication Interface (SCI) 12.3.1 Receive Shift Register (SCRSR) SCRSR receives serial data. Data input at the RXD pin is loaded into SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to SCRDR.
Page 436: Transmit Data Register (Sctdr)
Section 12 Serial Communication Interface (SCI) 12.3.4 Transmit Data Register (SCTDR) SCTDR is an 8-bit register that stores data for serial transmission. When the SCI detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in the SCTDR into SCTSR and starts serial transmission.
Page 437 Section 12 Serial Communication Interface (SCI) Initial value Bit Name Description Character Length Selects 7-bit or 8-bit data in asynchronous mode. In the clock synchronous mode, the data length is always eight bits, regardless of the CHR setting. When 7-bit data is selected, the MSB (bit 7) of the transmit data register is not transmitted.
Page 438 Section 12 Serial Communication Interface (SCI) Initial value Bit Name Description STOP Stop Bit Length Selects one or two bits as the stop bit length in asynchronous mode. This setting is used only in asynchronous mode. It is ignored in clock synchronous mode because no stop bits are added.
Page 439: Serial Control Register (Scscr)
Section 12 Serial Communication Interface (SCI) 12.3.6 Serial Control Register (SCSCR) SCSCR is an 8-bit register that enables or disables SCI transmission/reception and interrupt requests and selects the transmit/receive clock source. The CPU can always read and write to SCSCR. Bit: MPIE TEIE...
Page 440 Section 12 Serial Communication Interface (SCI) Initial value Bit Name Description Transmit Enable Enables or disables the SCI serial transmitter. 0: Transmitter disabled* 1: Transmitter enabled* Notes: 1. The TDRE flag in SCSSR is fixed at 1. 2. Serial transmission starts after writing transmit data into SCTDR and clearing the TDRE flag in SCSSR to 0 while the transmitter is enabled.
Page 441 Section 12 Serial Communication Interface (SCI) Initial value Bit Name Description TEIE Transmit End Interrupt Enable Enables or disables a transmit end interrupt (TEI) to be issued when no valid transmit data is found in SCTDR during MSB data transmission. TEI can be canceled by clearing the TEND flag to 0 (by clearing the TDRE flag in SCSSR to 0 after reading TDRE = 1) or by clearing the TEIE bit to 0.
Page 442: Serial Status Register (Scssr)
Section 12 Serial Communication Interface (SCI) 12.3.7 Serial Status Register (SCSSR) SCSSR is an 8-bit register that contains status flags to indicate the SCI operating state. The CPU can always read and write to SCSSR, but cannot write 1 to status flags TDRE, RDRF, ORER, PER, and FER.
Page 443 Section 12 Serial Communication Interface (SCI) Initial value Bit Name Description RDRF R/(W)* Receive Data Register Full Indicates that the received data is stored in the receive data register (SCRDR). 0: Indicates that valid received data is not stored in SCRDR [Clearing conditions] •...
Page 444 Section 12 Serial Communication Interface (SCI) Initial value Bit Name Description ORER R/(W)* Overrun Error Indicates that an overrun error occurred during reception, causing abnormal termination. 0: Indicates that reception is in progress or was completed successfully* [Clearing conditions] • By a power-on reset or in standby mode •...
Page 445 Section 12 Serial Communication Interface (SCI) Initial value Bit Name Description R/(W)* Framing Error Indicates that a framing error occurred during data reception in asynchronous mode, causing abnormal termination. 0: Indicates that reception is in progress or was completed successfully* [Clearing conditions] •...
Page 446 Section 12 Serial Communication Interface (SCI) Initial value Bit Name Description R/(W)* Parity Error Indicates that a parity error occurred during data reception in asynchronous mode, causing abnormal termination. 0: Indicates that reception is in progress or was completed successfully* [Clearing conditions] •...
Page 447 Section 12 Serial Communication Interface (SCI) Initial value Bit Name Description TEND Transmit End Indicates that no valid data was in SCTDR during transmission of the last bit of the transmit character and transmission has ended. The TEND flag is read-only and cannot be modified. 0: Indicates that transmission is in progress [Clearing condition] •...
Page 448: Serial Port Register (Scsptr)
Section 12 Serial Communication Interface (SCI) 12.3.8 Serial Port Register (SCSPTR) SCSPTR is an 8-bit register that controls input/output and data for the ports multiplexed with the SCI function pins. Data to be output through the TXD pin can be specified to control break of serial transfer.
Page 449 Section 12 Serial Communication Interface (SCI) Initial value Bit Name Description SPB1DT Clock Port Data in Serial Port Specifies the data output through the SCK pin in the serial port. Output should be enabled by the SPB1IO bit (for details, refer to the SPB1IO bit description). When output is enabled, the SPB1DT bit value is output through the SCK pin.
Page 450: Serial Direction Control Register (Scsdcr)
Section 12 Serial Communication Interface (SCI) 12.3.9 Serial Direction Control Register (SCSDCR) The DIR bit in the serial direction control register (SCSDCR) selects LSB-first or MSB-first transfer. With an 8-bit data length, LSB-first/MSB-first selection is available regardless of the communication mode. Bit: Initial value: R/W:...
Page 451: Bit Rate Register (Scbrr)
Section 12 Serial Communication Interface (SCI) 12.3.10 Bit Rate Register (SCBRR) SCBRR is an 8-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate.
Page 452 Section 12 Serial Communication Interface (SCI) Table 12.3 SCSMR Settings SCSMR Settings Clock Source CKS1 CKS0 Pφ Pφ/4 Pφ/16 Pφ/64 Note: The bit rate error in asynchronous is given by the following formula: Pφ × 10 × 100 Error (%) = (N + 1) ×...
Page 453 Section 12 Serial Communication Interface (SCI) Tables 12.4 to 12.6 show examples of SCBRR settings in asynchronous mode, and tables 12.7 to 12.9 show examples of SCBRR settings in clock synchronous mode. Table 12.4 Bit Rates and SCBRR Settings in Asynchronous Mode (1) Pφ...
Page 454 Section 12 Serial Communication Interface (SCI) Table 12.5 Bit Rates and SCBRR Settings in Asynchronous Mode (2) Pφ (MHz) Rate Error Error Error Error Error Error (bits/s) 3 97 -0.35 3 106 -0.44 3 114 0.36 3 123 0.23 3 132 0.13 3 141 0.03 3 71 -0.54...
Page 455 Section 12 Serial Communication Interface (SCI) Table 12.6 Bit Rates and SCBRR Settings in Asynchronous Mode (3) Pφ (MHz) Rate Error Error Error Error (bits/s) -0.05 -0.12 -0.19 -0.25 -0.29 0.16 -0.24 0.16 0.16 0.16 0.16 0.16 -0.29 0.16 -0.24 0.16 1200 0.16...
Page 456 Section 12 Serial Communication Interface (SCI) Table 12.7 Bit Rates and SCBRR Settings in Clock Synchronous Mode (1) Pφ (MHz) Bit Rate (bits/s) 1000 2500 5000 10000 25000 50000 100000 250000 500000       1000000  ...
Page 457 Section 12 Serial Communication Interface (SCI) Table 12.8 Bit Rates and SCBRR Settings in Clock Synchronous Mode (2) Pφ (MHz) Bit Rate (bits/s) 1000 2500 5000 10000 25000 50000 100000 250000 500000       1000000  ...
Page 458 Section 12 Serial Communication Interface (SCI) Table 12.9 Bit Rates and SCBRR Settings in Clock Synchronous Mode (3) Pφ (MHz) Bit Rate (bits/s) 1000 2500 5000 10000 25000 50000 100000 250000 500000     1000000    ...
Page 459 Section 12 Serial Communication Interface (SCI) Table 12.10 indicates the maximum bit rates in asynchronous mode when the baud rate generator is used. Tables 12.11 and 12.12 list the maximum rates for external clock input. Table 12.10 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings Pφ...
Page 460 Section 12 Serial Communication Interface (SCI) Table 12.11 Maximum Bit Rates with External Clock Input (Asynchronous Mode) Pφ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2.5000 156250 3.0000 187500 3.5000 218750 4.0000 250000 4.5000 281250 5.0000 312500 5.5000 343750 6.0000 375000...
Page 461 Section 12 Serial Communication Interface (SCI) Table 12.12 Maximum Bit Rates with External Clock Input (Clock Synchronous Mode) Pφ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 1.6667 1666666.7 2.0000 2000000.0 2.3333 2333333.3 2.6667 2666666.7 3.0000 3000000.0 3.3333 3333333.3 3.6667 3666666.7 4.0000...
Page 462: Operation
Section 12 Serial Communication Interface (SCI) 12.4 Operation 12.4.1 Overview For serial communication, the SCI has an asynchronous mode in which characters are synchronized individually, and a clock synchronous mode in which communication is synchronized with clock pulses. Asynchronous or clock synchronous mode is selected and the transmit format is specified in the serial mode register (SCSMR) as shown in table 12.13.
Page 463 Section 12 Serial Communication Interface (SCI) Table 12.13 SCSMR Settings and SCI Communication Formats SCSMR Settings SCI Communication Format Bit 7 Bit 6 Bit 5 Bit 3 Stop Bit STOP Mode Length Data Length Parity Bit Asynchronous 8-bit Not set 1 bit 2 bits 1 bit...
Page 464: Operation In Asynchronous Mode
Section 12 Serial Communication Interface (SCI) 12.4.2 Operation in Asynchronous Mode In asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible.
Page 465 Section 12 Serial Communication Interface (SCI) Transmit/Receive Formats Table 12.15 shows the transfer formats that can be selected in asynchronous mode. Any of 12 transfer formats can be selected according to the SCSMR settings. Table 12.15 Serial Transfer Formats (Asynchronous Mode) SCSMR Settings Serial Transfer Format and Frame Length STOP...
Page 466 Section 12 Serial Communication Interface (SCI) Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in the serial mode register (SCSMR) and bits CKE1 and CKE0 in the serial control register (SCSCR) (table 12.14).
Page 467 Section 12 Serial Communication Interface (SCI) [1] Set the clock selection in SCSCR. Start initialization [2] Set the data transfer format in SCSMR and SCSDCR. [3] Write a value corresponding to the bit Clear RIE, TIE, TEIE, MPIE, rate to SCBRR. Not necessary if an TE, and RE bits in SCSCR to 0* external clock is used.
Page 468 Section 12 Serial Communication Interface (SCI) Transmitting Serial Data (Asynchronous Mode): Figure 12.4 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCI for transmission. Start of transmission [1] SCI status check and transmit data write: Read TDRE flag in SCSSR Read SCSSR and check that the...
Page 469 Section 12 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in the serial status register (SCSSR). If it is cleared to 0, the SCI recognizes that data has been written to the transmit data register (SCTDR) and transfers the data from SCTDR to the transmit shift register (SCTSR).
Page 470 Section 12 Serial Communication Interface (SCI) Figure 12.5 shows an example of the operation for transmission. Start Data Parity Stop Start Data Parity Stop Serial Idle state data (mark state) TDRE TEND TXI interrupt TXI interrupt request request TEI interrupt Data written to SCTDR request and TDRE flag cleared to 0...
Page 471 Section 12 Serial Communication Interface (SCI) Receiving Serial Data (Asynchronous Mode): Figure 12.6 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCI for reception. [1] Receive error handling and break Start of reception detection: If a receive error occurs, read the ORER,...
Page 472 Section 12 Serial Communication Interface (SCI) Error processing ORER = 1? Overrun error processing FER = 1? Break? Framing error processing Clear RE bit in SCSCR to 0 PER = 1? Parity error processing Clear ORER, PER, and FER flags in SCSSR to 0 <End>...
Page 473 Section 12 Serial Communication Interface (SCI) In serial reception, the SCI operates as described below. 1. The SCI monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR in LSB-to-MSB order. 3.
Page 474: Clock Synchronous Mode (Channel 1 In The Sh7124 Is Not Available)
Section 12 Serial Communication Interface (SCI) Figure 12.7 shows an example of the operation for reception. Start Data Parity Stop Start Data Parity Stop Serial data RDRF RXI interrupt request Data read and RDRF flag ERI interrupt request cleared to 0 by RXI generated by framing One frame interrupt handler...
Page 475 Section 12 Serial Communication Interface (SCI) In clock synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock.
Page 476 Section 12 Serial Communication Interface (SCI) Figure 12.9 shows a sample flowchart for initializing the SCI. Set the clock selection in SCSCR. Start initialization Set the data transfer format in SCSMR. Write a value corresponding to the bit rate to Clear RIE, TIE, TEIE, MPIE, SCBRR.
Page 477 Section 12 Serial Communication Interface (SCI) Transmitting Serial Data (Clock Synchronous Mode): Figure 12.10 shows a sample flowchart for transmitting serial data. Use the following procedure for serial data transmission after enabling the SCI for transmission. Start of transmission [1] SCI status check and transmit data write: Read TDRE flag in SCSSR Read SCSSR and check that the...
Page 478 Section 12 Serial Communication Interface (SCI) In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE flag in the serial status register (SCSSR). If it is cleared to 0, the SCI recognizes that data has been written to the transmit data register (SCTDR) and transfers the data from SCTDR to the transmit shift register (SCTSR).
Page 479 Section 12 Serial Communication Interface (SCI) Receiving Serial Data (Clock Synchronous Mode): Figure 12.12 shows a sample flowchart for receiving serial data. Use the following procedure for serial data reception after enabling the SCIF for reception. When switching from asynchronous mode to clock synchronous mode, make sure that the ORER, PER, and FER flags are all cleared to 0.
Page 480 Section 12 Serial Communication Interface (SCI) Error handling ORER = 1? Overrun error handling Clear ORER flag in SCSSR to 0 Figure 12.12 Sample Flowchart for Receiving Serial Data (2) In receiving, the SCI operates as follows: 1. The SCI synchronizes with serial clock input or output and initializes internally. 2.
Page 481 Section 12 Serial Communication Interface (SCI) Figure 12.13 shows an example of SCI receive operation. Transfer direction Synchronization clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt Data read from SCRDR and RXI interrupt ERI interrupt request request...
Page 482 Section 12 Serial Communication Interface (SCI) Start of transmission and reception SCI status check and transmit data write: Read SCSSR and check that the TDRE flag is set to 1, then write transmit data to SCTDR and Read TDRE flag in SCSSR clear the TDRE flag to 0.
Page 483: Multiprocessor Communication Function
Section 12 Serial Communication Interface (SCI) 12.4.4 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data.
Page 484 Section 12 Serial Communication Interface (SCI) Transmitting station Serial transmission line Receiving Receiving Receiving Receiving station A station B station C station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial H'01 H'AA data (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle =...
Page 485: Multiprocessor Serial Data Transmission
Section 12 Serial Communication Interface (SCI) 12.4.5 Multiprocessor Serial Data Transmission Figure 12.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SCSSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SCSSR to 0 before transmission.
Page 486: Multiprocessor Serial Data Reception
Section 12 Serial Communication Interface (SCI) 12.4.6 Multiprocessor Serial Data Reception Figure 12.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCSCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to SCRDR.
Page 487 Section 12 Serial Communication Interface (SCI) SCI initialization: Initialization Set the RXD pin using the PFC. Start reception ID reception cycle: Set the MPIE bit in SCSCR to 1. Set MPIE bit in SCSCR to 1 SCI status check, ID reception and comparison: Read ORER and FER flags Read SCSSR and check that the RDRF flag is...
Page 488 Section 12 Serial Communication Interface (SCI) Error processing ORER = 1 Overrun error processing FER = 1 Break? Framing error processing Clear RE bit in SCSCR to 0 Clear ORER and FER flags in SCSSR to 0 <End> Figure 12.18 Sample Multiprocessor Serial Reception Flowchart (2) Rev.
Page 489: Sci Interrupt Sources
Section 12 Serial Communication Interface (SCI) 12.5 SCI Interrupt Sources The SCI has four interrupt sources: transmit end (TEI), receive error (ERI), receive-data-full (RXI), and transmit-data-empty (TXI) interrupt requests. Table 12.17 shows the interrupt sources. The interrupt sources are enabled or disabled by means of the TIE, RIE, and TEIE bits in SCSCR and the EIO bit in SCSPTR.
Page 490: Serial Port Register (Scsptr) And Sci Pins
Section 12 Serial Communication Interface (SCI) 12.6 Serial Port Register (SCSPTR) and SCI Pins The relationship between SCSPTR and the SCI pins is shown in figures 12.19 and 12.20. Reset Bit 3 SCKIO Internal data bus SPTRW Reset Bit 2 SCKDT SPTRW Clock output enable signal*...
Page 491: Usage Notes
Section 12 Serial Communication Interface (SCI) 12.7 Usage Notes 12.7.1 SCTDR Writing and TDRE Flag The TDRE flag in the serial status register (SCSSR) is a status flag indicating transferring of transmit data from SCTDR into SCTSR. The SCI sets the TDRE flag to 1 when it transfers data from SCTDR to SCTSR.
Page 492: Break Detection And Processing
Section 12 Serial Communication Interface (SCI) 12.7.3 Break Detection and Processing Break signals can be detected by reading the RXD pin directly when a framing error (FER) is detected. In the break state the input from the RXD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set.
Page 493 Section 12 Serial Communication Interface (SCI) 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 6 7 8 9 10 1112 1314 15 0 1 2 3 4 5 Base clock –7.5 clocks +7.5 clocks...
Page 494: Note On Using External Clock In Clock Synchronous Mode
Section 12 Serial Communication Interface (SCI) 12.7.6 Note on Using External Clock in Clock Synchronous Mode TE and RE must be set to 1 after waiting for four or more cycles of the peripheral operating clock after the SCK external clock is changed from 0 to 1. TE and RE must be set to 1 only while the SCK external clock is 1.
Page 495: Section 13 A/D Converter (Adc)
Section 13 A/D Converter (ADC) Section 13 A/D Converter (ADC) This LSI includes a successive approximation type 10-bit A/D converter. 13.1 Features • 10-bit resolution • Input channels  8 channels (two independent A/D conversion modules) • Conversion time: 2.0 µs per channel (preliminary value, operation when Pφ = 25 MHz) •...
Page 496 Section 13 A/D Converter (ADC) Figure 13.1 shows a block diagram of the A/D converter. Module data bus Internal data bus 10-bit D/A Pφ Pφ/2 • Comparator Control circuit Pφ/3 • • Sample-and- Pφ/4 hold circuit • • • interrupt signal Conversion start trigger from MTU2 ADTRG...
Page 497: Input/Output Pins
Section 13 A/D Converter (ADC) 13.2 Input/Output Pins Table 13.1 summarizes the input pins used by the A/D converter. This LSI has two A/D conversion modules, each of which can be operated independently. The input channels of A/D modules 0 and 1 are divided into two channel groups. Table 13.1 Pin Configuration Module Type Symbol...
Page 498: Register Descriptions
Section 13 A/D Converter (ADC) 13.3 Register Descriptions The A/D converter has the following registers. For details on register addresses and register states in each processing state, refer to section 20, List of Registers. Table 13.2 Register Configuration Abbrevia- Register Name tion Initial Value Address...
Page 499: A/D Data Registers 0 To 7 (Addr0 To Addr7)
Section 13 A/D Converter (ADC) 13.3.1 A/D Data Registers 0 to 7 (ADDR0 to ADDR7) ADDRs are 16-bit read-only registers. The conversion result for each analog input channel is stored in ADDR with the corresponding number. (For example, the conversion result of AN4 is stored in ADDR4.) The converted 10-bit data is stored in bits 6 to 15.
Page 500 Section 13 A/D Converter (ADC) Initial Value Bit Name Description ADIE A/D Interrupt Enable The A/D conversion end interrupt (ADI) request is enabled when 1 is set When changing the operating mode, first clear the ADST bit to 0.  13, 12 All 0 Reserved...
Page 501 Section 13 A/D Converter (ADC) Initial Value Bit Name Description State Control Sets the A/D conversion time in combination with the CKSL1 and CKSL0 bits. 0: 50 states 1: 64 states When changing the A/D conversion time, first clear the ADST bit to 0.
Page 502: A/D Control Registers_0 And _1 (Adcr_0 And Adcr_1)
Section 13 A/D Converter (ADC) Initial Value Bit Name Description 2 to 0 CH[2:0] Channel Select 2 to 0 Select analog input channels. See table 13.3. When changing the operating mode, first clear the ADST bit to 0. Note: * Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way. 13.3.3 A/D Control Registers_0 and _1 (ADCR_0 and ADCR_1) ADCR for each module controls A/D conversion.
Page 503 Section 13 A/D Converter (ADC) Table 13.3 Channel Select List Analog Input Channels Bit 2 Bit 1 Bit 0 Single Mode 4-Channel Scan Mode* A/D_0 A/D_1 A/D_0 A/D_1 AN0, AN1 AN4, AN5 AN0 to AN2 AN4 to AN6 AN0 to AN3 AN4 to AN7 Setting prohibited Setting prohibited...
Page 504: A/D Trigger Select Register_0 (Adtsr_0)
Section 13 A/D Converter (ADC) 13.3.4 A/D Trigger Select Register_0 (ADTSR_0) The ADTSR_0 enables an A/D conversion started by an external trigger signal. In particular, the four channels in A/D module 0 are divided into two groups (group 0 and group 1) and the A/D trigger can be specified for each group independently in 2-channel scan mode.
Page 505 Section 13 A/D Converter (ADC) Initial Value Bit Name Description 11 to 8 TRG01S[3:0] 0000 A/D Trigger 0 Group 1 Select 3 to 0 Select an external trigger or MTU2 trigger to start A/D conversion for group 1 when A/D module 0 is in 2- channel scan mode.
Page 506 Section 13 A/D Converter (ADC) Initial Value Bit Name Description 7 to 4 TRG1S[3:0] 0000 A/D Trigger 1 Select 3 to 0 Select an external trigger or MTU2 trigger to start A/D conversion for group 0 when A/D module 1 is in single mode, 4-channel scan mode, or 2-channel scan mode.
Page 507 Section 13 A/D Converter (ADC) Initial Value Bit Name Description 3 to 0 TRG0S[3:0] 0000 A/D Trigger 0 Select 3 to 0 Select an external trigger or MTU2 trigger to start A/D conversion for group 0 when A/D module 0 is in single mode, 4-channel scan mode, or 2-channel scan mode.
Page 508: Operation
Section 13 A/D Converter (ADC) 13.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. There are two kinds of scan mode: continuous mode and single-cycle mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the ADST bit to 0 in ADCR.
Page 509: Single-Cycle Scan Mode
Section 13 A/D Converter (ADC) 13.4.3 Single-Cycle Scan Mode In single-cycle scan mode, A/D conversion is to be performed once on the specified channels (up to four channels). 1. When the ADST bit in ADCR is set to 1 by a software, MTU2, or external trigger input, A/D conversion starts on the channel with the lowest number in the group (AN0, AN1, ..., AN3).
Page 510 Section 13 A/D Converter (ADC) A/D conversion time (t CONV A/D conversion start Analog input delay time(t sampling time(t Write cycle A/D synchronization time (2 states) (Up to 6 states) Pφ Address Internal write signal ADST write timing Analog input sampling signal Idle state...
Page 511 Section 13 A/D Converter (ADC) Table 13.4 A/D Conversion Time (Single Mode) STC = 0 CKSL1 = 0 CKSL1 = 1 CKSL0 = 0 CKSL0 = 1 CKSL0 = 0 CKSL0 = 1 Item Symbol Min. Typ. Max. Min. Typ. Max. Min.
Page 512: A/D Converter Activation By Mtu2
Section 13 A/D Converter (ADC) 13.4.5 A/D Converter Activation by MTU2 The A/D converter can be independently activated by an A/D conversion request from the interval timer of the MTU2. To activate the A/D converter by the MTU2, first set the TRGE bit in the A/D control/status register (ADCSR) to 1, and then set the A/D trigger select register (ADTSR).
Page 513: 2-Channel Scanning
Section 13 A/D Converter (ADC) 13.4.7 2-Channel Scanning In 2-channel scan mode, since the four channels of analog input are divided into groups 0 and 1, triggers for activation of groups 0 and 1 are independently specifiable. Conversion end interrupts in 2-channel scan mode can be generated either on completion of group 0 or group 1 or on completion of group 0 and group 1.
Page 514: Interrupt Sources
Section 13 A/D Converter (ADC) 13.5 Interrupt Sources The A/D converter can generate an A/D conversion end interrupt request. The ADI interrupt can be enabled by setting the ADIE bit in the A/D control/status register (ADCSR) to 1, or disabled by clearing the ADIE bit to 0.
Page 515: Definitions Of A/D Conversion Accuracy
Section 13 A/D Converter (ADC) 13.6 Definitions of A/D Conversion Accuracy This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 13.5). •...
Page 516 Section 13 A/D Converter (ADC) Digital output Ideal A/D conversion characteristic Quantization error 1022 1023 1024 1024 1024 1024 Analog input voltage Figure 13.5 Definitions of A/D Conversion Accuracy Rev. 3.00 Sep. 27, 2007 Page 496 of 758 REJ09B0243-0300...
Page 517 Section 13 A/D Converter (ADC) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Analog Offset error input voltage Figure 13.6 Definitions of A/D Conversion Accuracy Rev. 3.00 Sep. 27, 2007 Page 497 of 758 REJ09B0243-0300...
Page 518: Usage Notes
Section 13 A/D Converter (ADC) 13.7 Usage Notes 13.7.1 Module Standby Mode Setting Operation of the A/D converter can be disabled or enabled using the standby control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module standby mode.
Page 519: Range Of Analog Power Supply And Other Pin Settings
Section 13 A/D Converter (ADC) This LSI Sensor output A/D converter impedance of equivalent circuit up to 3 kΩ or up to 1 kΩ 10 kΩ Sensor input Low-pass 20 pF 20 pF filter C to 0.1 µF Figure 13.7 Example of Analog Input Circuit 13.7.4 Range of Analog Power Supply and Other Pin Settings If the conditions below are not met, the reliability of the device may be adversely affected.
Page 520: Notes On Noise Countermeasures
Section 13 A/D Converter (ADC) 13.7.6 Notes on Noise Countermeasures A protection circuit should be connected in order to prevent damage due to abnormal voltage, such as an excessive surge at the analog input pins (AN0 to AN7), between AVcc and AVss, as shown in figure 13.8.
Page 521: Section 14 Compare Match Timer (Cmt)
Section 14 Compare Match Timer (CMT) Section 14 Compare Match Timer (CMT) This LSI has an on-chip compare match timer (CMT) consisting of a 2-channel 16-bit timer. The CMT has a16-bit counter, and can generate interrupts at set intervals. 14.1 Features •...
Page 522: Register Descriptions
Section 14 Compare Match Timer (CMT) 14.2 Register Descriptions The CMT has the following registers. For details on register addresses and register states during each processing, refer to section 20, List of Registers. Note that the channel number is omitted from the register name in this section.
Page 523: Compare Match Timer Start Register (Cmstr)
Section 14 Compare Match Timer (CMT) 14.2.1 Compare Match Timer Start Register (CMSTR) CMSTR is a 16-bit register that selects whether compare match counter (CMCNT) operates or is stopped. Bit: STR1 STR0 Initial value: R/W: Initial Bit Name value Description ...
Page 524 Section 14 Compare Match Timer (CMT) Initial value Bit Name Description  15 to 8 All 0 Reserved These bits are always read as 0. The write value should always be 0. R/(W)* Compare Match Flag Indicates whether or not the values of CMCNT and CMCOR match.
Page 525: Compare Match Counter (Cmcnt)
Section 14 Compare Match Timer (CMT) 14.2.3 Compare Match Counter (CMCNT) CMCNT is a 16-bit register used as an up-counter. When the counter input clock is selected with bits CKS1 and CKS0 in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts counting using the selected clock.
Page 526: Operation
Section 14 Compare Match Timer (CMT) 14.3 Operation 14.3.1 Interval Count Operation When an internal clock is selected with bits CKS1 and CKS0 in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1.
Page 527: Interrupts
Section 14 Compare Match Timer (CMT) 14.4 Interrupts 14.4.1 CMT Interrupt Sources The CMT has channels and each of them to which a different vector address is allocated has compare match interrupt. When both the interrupt request flag (CMF) and interrupt enable bit (CMIE) are set to 1, the corresponding interrupt request is output.
Page 528: Usage Notes
Section 14 Compare Match Timer (CMT) 14.5 Usage Notes 14.5.1 Module Standby Mode Setting The CMT operation can be disabled or enabled using the standby control register. The initial setting is for CMT operation to be halted. Access to a register is enabled by clearing module standby mode.
Page 529: Conflict Between Word-Write And Count-Up Processes Of Cmcnt
Section 14 Compare Match Timer (CMT) 14.5.3 Conflict between Word-Write and Count-Up Processes of CMCNT Even when the count-up occurs in the T2 cycle while writing to CMCNT in words, the writing has priority over the count-up. In this case, the count-up is not performed. Figure 14.6 shows the timing to write to CMCNT in words.
Page 530: Conflict Between Byte-Write And Count-Up Processes Of Cmcnt
Section 14 Compare Match Timer (CMT) 14.5.4 Conflict between Byte-Write and Count-Up Processes of CMCNT Even when the count-up occurs in the T2 cycle while writing to CMCNT in bytes, the byte-writing has priority over the count-up. In this case, the count-up is not performed. The byte data on another side, which is not written to, is also not counted and the previous contents remain.
Page 531: Section 15 Pin Function Controller (Pfc)
Section 15 Pin Function Controller (PFC) Section 15 Pin Function Controller (PFC) The pin function controller (PFC) is composed of registers that are used to select the functions of multiplexed pins and assign pins to be inputs or outputs. Tables 15.1 and 15.2 list the multiplexed pins of this LSI.
Page 532 Section 15 Pin Function Controller (PFC) Function 1 Function 2 Function 3 Function 4 Function 5 Port (Related Module) (Related Module) (Related Module) (Related Module) (Related Module)    PE0 I/O (port) TIOC0A I/O (MTU2)   PE1 I/O (port) TIOC0B I/O (MTU2) RXD0 input (SCI) ...
Page 533 Section 15 Pin Function Controller (PFC) Table 15.2 SH7124 Multiplexed Pins Function 1 Function 2 Function 3 Function 4 Function 5 Port (Related Module) (Related Module) (Related Module) (Related Module) (Related Module) POE0 input (POE)   PA0 I/O (port) RXD0 input (SCI) POE1 input (POE) ...
Page 534 Section 15 Pin Function Controller (PFC) Function 1 Function 2 Function 3 Function 4 Function 5 Port (Related Module) (Related Module) (Related Module) (Related Module) (Related Module)    PF0 input (port) AN0 input (A/D)    PF1 input (port) AN1 input (A/D) ...
Page 535 Section 15 Pin Function Controller (PFC) Table 15.3 SH7125 Pin Functions in Each Operating Mode Pin Name Single-Chip Mode (MCU Mode 3) Pin No. Initial Function PFC Selected Function Possibilities 4, 22, 35 6, 24, 33 8, 37 AVcc AVcc AVss AVss PLLVss...
Page 536 Section 15 Pin Function Controller (PFC) Pin Name Single-Chip Mode (MCU Mode 3) Pin No. Initial Function PFC Selected Function Possibilities PA14 PA14/RXD1 PA15 PA15/TXD1 PB1/TIC5W PB2/IRQ0/POE0 PB3/IRQ1/POE1/TIC5V PB5/IRQ3/TIC5U POE3 PB16/POE3 PE0/TIOC0A PE1/TIOC0B/RXD0 PE2/TIOC0C/TXD0 PE3/TIOC0D/SCK0 PE4/TIOC1A/RXD1 PE5/TIOC1B/TXD1 PE6/TIOC2A/SCK1 PE7/TIOC2B PE8/TIOC3A PE9/TIOC3B PE10 PE10/TIOC3C...
Page 537 Section 15 Pin Function Controller (PFC) Pin Name Single-Chip Mode (MCU Mode 3) Pin No. Initial Function PFC Selected Function Possibilities PF6/AN6 PF6/AN6 PF7/AN7 PF7/AN7 * Fixed to TMS, TRST, TDI, TDO, TCK, and ASEBRKAK/ASEBRK when using the E10A Note: (in ASEMD0 = low).
Page 538 Section 15 Pin Function Controller (PFC) Pin Name Single-Chip Mode (MCU Mode 3) Pin No. Initial Function PFC Selected Function Possibilities PA8/(TDI*) PA8/TCLKC/RXD2 PA9/(TDO*) PA9/TCLKD/TXD2/POE8 PB1/TIC5W PB3/IRQ1/POE1/TIC5V PB5/IRQ3/TIC5U PE0/TIOC0A PE1/TIOC0B/RXD0 PE2/TIOC0C/TXD0 PE3/TIOC0D/SCK0 PE8/TIOC3A PE9/TIOC3B PE10 PE10/TIOC3C PE11 PE11/TIOC3D PE12 PE12/TIOC4A PE13 PE13/TIOC4B/MRES PE14...
Page 539: Register Descriptions
Section 15 Pin Function Controller (PFC) 15.1 Register Descriptions The PFC has the following registers. For details on register addresses and register states in each processing state, refer to section 20, List of Registers. Table 15.5 Register Configuration Abbrevia- Register Name tion Initial Value Address...
Page 540: Port A I/O Register L (Paiorl)
Section 15 Pin Function Controller (PFC) 15.1.1 Port A I/O Register L (PAIORL) PAIORL is a 16-bit readable/writable register that is used to set the pins on port A as inputs or outputs. Bits PA15IOR to PA0IOR correspond to pins PA15 to PA0 (names of multiplexed pins are here given as port names and pin numbers alone).
Page 541 Section 15 Pin Function Controller (PFC) Initial Value Bit Name Description PA15MD2 PA15 Mode PA15MD1 Select the function of the PA15/TXD1 pin. PA15MD0 000: PA15 I/O (port) 110: TXD1 output (SCI) Other than above: Setting prohibited  Reserved This bit is always read as 0. The write value should always be 0.
Page 542 Section 15 Pin Function Controller (PFC) • Port A Control Register L3 (PACRL3) Bit: PA11 PA11 PA11 PA10 PA10 PA10 Initial value: R/W: Initial Bit Name Value Description  Reserved This bit is always read as 0. The write value should always be 0.
Page 543 Section 15 Pin Function Controller (PFC) Initial Value Bit Name Description PA9MD2 PA9 Mode PA9MD1 Select the function of the PA9/TCLKD/TXD2/TDO/POE8 pin. PA9MD0 When the E10A is in use (ASEMD0 = low), function is fixed to TDO output. 000: PA9 I/O (port) 001: TCLKD input (MTU2) 110: TXD2 output (SCI) 111: POE8 input (POE)
Page 544 Section 15 Pin Function Controller (PFC) • Port A Control Register L2 (PACRL2) Bit: Initial value: R/W: Initial Bit Name Value Description  Reserved This bit is always read as 0. The write value should always be 0. PA7MD2 PA7 Mode PA7MD1 Select the function of the PA7/TCLKB/SCK2/TCK pin.
Page 545 Section 15 Pin Function Controller (PFC) Initial Value Bit Name Description  Reserved This bit is always read as 0. The write value should always be 0. PA4MD2 PA4 Mode PA4MD1 Select the function of the PA4/IRQ2/TXD1/TMS pin. When the E10A is in use (ASEMD0 = low), function is PA4MD0 fixed to TCK input.
Page 546 Section 15 Pin Function Controller (PFC) Initial Value Bit Name Description PA2MD2 PA2 Mode PA2MD1 Select the function of the PA2/IRQ0/SCK0 pin. PA2MD0 000: PA2 I/O (port) 001: SCK0 I/O (SCI) 011: IRQ0 input (INTC) Other than above: Setting prohibited ...
Page 547 Section 15 Pin Function Controller (PFC) SH7124: • Port A Control Register L4 (PACRL4) Bit: Initial value: R/W: Initial Bit Name Value Description  15 to 0 All 0 Reserved These bits are always read as 0. The write value should always be 0.
Page 548 Section 15 Pin Function Controller (PFC) Initial Value Bit Name Description PA8MD2 PA8 Mode PA8MD1 Select the function of the PA8/TCLKC/RXD2/TDI pin. When the E10A is in use (ASEMD0 = low), function is PA8MD0 fixed to TDI input. 000: PA8 I/O (port) 001: TCLKC input (MTU2) 110: RXD2 input (SCI) Other than above: Setting prohibited...
Page 549 Section 15 Pin Function Controller (PFC) Initial Value Bit Name Description PA6MD2 PA6 Mode PA6MD1 Select the function of the PA6/TCLKA pin. PA6MD0 000: PA6 I/O (port) 001: TCLKA input (MTU2) Other than above: Setting prohibited  7 to 3 All 0 Reserved These bits are always read as 0.
Page 550 Section 15 Pin Function Controller (PFC) Initial Value Bit Name Description PA3MD2 PA3 Mode PA3MD1 Select the function of the PA3/IRQ1/RXD1/TRST pin. When the E10A is in use (ASEMD0 = low), function is PA3MD0 fixed to TRST input. 000: PA3 I/O (port) 001: RXD1 input (SCI) 111: IRQ1 input (INTC) Other than above: Setting prohibited...
Page 551: Port B I/O Registers L And H (Pbiorl And Pbiorh)
Section 15 Pin Function Controller (PFC) 15.1.3 Port B I/O Registers L and H (PBIORL and PBIORH) PBIORL and PBIORH are 16-bit readable/writable registers that are used to set the pins on port B as inputs or outputs. Bits PB16IOR, PB5IOR, and PB3IOR to PB1IOR correspond to pins PB16, PB5, and PB3 to PB1, respectively (names of multiplexed pins are here given as port names and pin numbers alone).
Page 552: Port B Control Registers L1, L2, And H1 (Pbcrl1, Pbcrl2, And Pbcrh1)
Section 15 Pin Function Controller (PFC) 15.1.4 Port B Control Registers L1, L2, and H1 (PBCRL1, PBCRL2, and PBCRH1) PBCRL1, PBCRL2, and PBCRH1 are 16-bit readable/writable registers that are used to select the function of the multiplexed pins on port B. SH7125: •...
Page 553 Section 15 Pin Function Controller (PFC) Initial Value Bit Name Description PB5MD2 PB5 Mode PB5MD1 Select the function of the PB5/IRQ3/TIC5U pin. PB5MD0 000: PB5 I/O (port) 001: IRQ3 input (INTC) 011: TIC5U input (MTU2) Other than above: Setting prohibited ...
Page 554 Section 15 Pin Function Controller (PFC) Initial Value Bit Name Description PB2MD2 PB2 Mode PB2MD1 Select the function of the PB2/IRQ0/POE0 pin. PB2MD0 000: PB2 I/O (port) 001: IRQ0 input (INTC) 010: POE0 input (POE) Other than above: Setting prohibited ...
Page 555 Section 15 Pin Function Controller (PFC) • Port B Control Register L2 (PBCRL2) Bit: Initial value: R/W: Initial Bit Name Value Description  15 to 7 All 0 Reserved These bits are always read as 0. The write value should always be 0. PB5MD2 PB5 Mode PB5MD1...
Page 556 Section 15 Pin Function Controller (PFC) Initial Value Bit Name Description PB3MD2 PB3 Mode PB3MD1 Select the function of the PB3/IRQ1/POE1/TIC5V pin. PB3MD0 000: PB3 I/O (port) 001: IRQ1 input (INTC) 010: POE1 input (POE) 011: TIC5V input (MTU2) Other than above: Setting prohibited ...
Page 557: Port E I/O Register L (Peiorl)
Section 15 Pin Function Controller (PFC) 15.1.5 Port E I/O Register L (PEIORL) PEIORL is a 16-bit readable/writable register that is used to set the pins on port E as inputs or outputs. PE15IOR to PE0IOR correspond to pins PE15 to PE0 (names of multiplexed pins are here given as port names and pin numbers alone).
Page 558 Section 15 Pin Function Controller (PFC) Initial Value Bit Name Description PE15MD2 PE15 Mode PE15MD1 Select the function of the PE15/TIOC4D/IRQOUT pin. PE15MD0 000: PE15 I/O (port) 001: TIOC4D I/O (MTU2) 011: IRQOUT output (INTC) Other than above: Setting prohibited ...
Page 559 Section 15 Pin Function Controller (PFC) • Port E Control Register L3 (PECRL3) Bit: PE11 PE11 PE11 PE10 PE10 PE10 Initial value: R/W: Initial Bit Name Value Description  Reserved This bit is always read as 0. The write value should always be 0.
Page 560 Section 15 Pin Function Controller (PFC) Initial Value Bit Name Description PE8MD2 PE8 Mode PE8MD1 Select the function of the PE8/TIOC3A pin. PE8MD0 000: PE8 I/O (port) 001: TIOC3A I/O (MTU2) Other than above: Setting prohibited • Port E Control Register L2 (PECRL2) Bit: Initial value: R/W:...
Page 561 Section 15 Pin Function Controller (PFC) Initial Value Bit Name Description  Reserved This bit is always read as 0. The write value should always be 0. PE5MD2 PE5 Mode PE5MD1 Select the function of the PE5/TIOC1B/TXD1 pin. PE5MD0 000: PE5 I/O (port) 001: TIOC1B I/O (MTU2) 110: TXD1 output (SCI) Other than above: Setting prohibited...
Page 562 Section 15 Pin Function Controller (PFC) Initial Value Bit Name Description PE3MD2 PE3 Mode PE3MD1 Select the function of the PE3/TIOC0D/SCK0 pin. PE3MD0 000: PE3 I/O (port) 001: TIOC0D I/O (MTU2) 110: SCK0 I/O (SCI) Other than above: Setting prohibited ...
Page 563 Section 15 Pin Function Controller (PFC) SH7124: • Port E Control Register L4 (PECRL4) Bit: PE15 PE15 PE15 PE14 PE14 PE14 PE13 PE13 PE12 PE12 PE12 Initial value: R/W: Initial Value Bit Name Description  Reserved This bit is always read as 0. The write value should always be 0.
Page 564 Section 15 Pin Function Controller (PFC) Initial Value Bit Name Description  Reserved This bit is always read as 0. The write value should always be 0. PE12MD2 PE12 Mode PE12MD1 Select the function of the PE12/TIOC4A pin. PE12MD0 000: PE12 I/O (port) 001: TIOC4A I/O (MTU2) Other than above: Setting prohibited •...
Page 565 Section 15 Pin Function Controller (PFC) Initial Value Bit Name Description  Reserved This bit is always read as 0. The write value should always be 0. PE9MD2 PE9 Mode PE9MD1 Select the function of the PE9/TIOC3B pin. PE9MD0 000: PE9 I/O (port) 001: TIOC3B I/O (MTU2) Other than above: Setting prohibited ...
Page 566 Section 15 Pin Function Controller (PFC) • Port E Control Register L1 (PECRL1) Bit: Initial value: R/W: Initial Bit Name Value Description  Reserved This bit is always read as 0. The write value should always be 0. PE3MD2 PE3 Mode PE3MD1 Select the function of the PE3/TIOC0D/SCK0 pin.
Page 567: Irqout Function Control Register
Section 15 Pin Function Controller (PFC) Initial Value Bit Name Description  3, 2 All 0 Reserved These bits are always read as 0. The write value should always be 0. PE0MD1 PE0 Mode PE0MD0 Select the function of the PE0/TIOC0A pin. 00: PE0 I/O (port) 01: TIOC0A I/O (MTU2) Other than above: Setting prohibited...
Page 568: Usage Notes
Section 15 Pin Function Controller (PFC) 15.2 Usage Notes 1. In this LSI, the same function is available as a multiplexed function on multiple pins. This approach is intended to increase the number of selectable pin functions and to allow the easier design of boards.
Page 569: Section 16 I/O Ports
Section 16 I/O Ports Section 16 I/O Ports The SH7125 has four ports: A, B, E, and F. Port A is a 16-bit port, port B is a 5-bit port, and port E is a 16-bit port. Port F is an 8-bit input-only port. The SH7124 has four ports: A, B, E, and F.
Page 570: Port A
Section 16 I/O Ports 16.1 Port A Port A in the SH7125 is an input/output port with the 16 pins shown in figure 16.1. PA15 (I/O)/ TXD1 (output) PA14 (I/O)/ RXD1 (input) PA13 (I/O)/ SCK1 (I/O) PA12 (I/O)/ SCK0 (I/O) PA11 (I/O)/ TXD0 (output)/ ADTRG (input) PA10 (I/O)/ RXD0 (input) PA9 (I/O)/ TCLKD (input)/ TXD2 (output)/ TDO (output)/ POE8 (input)
Page 571: Register Descriptions
Section 16 I/O Ports 16.1.1 Register Descriptions Port A is a 16-bit input/output port in the SH7125 and an 8-bit input/output port in the SH7124. Port A has the following registers. For details on register addresses and register states during each processing, refer to section 20, List of Registers.
Page 572 Section 16 I/O Ports • PADRL (SH7125) Bit: PA15 PA14 PA13 PA12 PA11 PA10 Initial value: R/W: Initial Bit Name Value Description PA15DR See table 16.2. PA14DR PA13DR PA12DR PA11DR PA10DR PA9DR PA8DR PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR Rev.
Page 573 Section 16 I/O Ports • PADRL (SH7124) Bit: Initial value: R/W: Initial Bit Name Value Description  15 to 10 All 0 Reserved These bits are always read as 0. The write value should always be 0. PA9DR See table 16.2. PA8DR PA7DR PA6DR...
Page 574 Section 16 I/O Ports Table 16.2 Port A Data Register L (PADRL) Read/Write Operations • PADRL Bits 15 to 0 PAIORH, PAIORL Pin Function Read Write General input Pin state Can write to PADRL, but it has no effect on pin state Other than Pin state...
Page 575: Port A Port Register L (Paprl)
Section 16 I/O Ports 16.1.3 Port A Port Register L (PAPRL) PAPRL is a 16-bit read-only register that always return the states of the pins regardless of the PFC setting. Bits PA15PR to PA0PR correspond to pins PA15 to PA0 (multiplexed functions omitted here) in the SH7125.
Page 576 Section 16 I/O Ports • PAPRL (SH7124) Bit: Initial value: R/W: Initial Bit Name Value Description  15 to 10 All 0 Reserved These bits are always read as 0. The write value should always be 0. PA9PR Pin state R The pin state is returned regardless of the PFC setting.
Page 577: Port B
Section 16 I/O Ports 16.2 Port B Port B in the SH7125 is an input/output port with the five pins shown in figure 16.3. PB16 (I/O)/ POE3 (input) PB5 (I/O)/ IRQ3 (input)/ TIC5U (input) PB3 (I/O)/ IRQ1 (input)/ POE1 (input)/ TIC5V (input) Port B PB2 (I/O)/I RQ0 (input)/ POE0 (input) PB1 (I/O)/ TIC5W (input)
Page 578: Port B Data Registers H And L (Pbdrh And Pbdrl)
Section 16 I/O Ports 16.2.2 Port B Data Registers H and L (PBDRH and PBDRL) PBDRH and PBDRL are 16-bit readable/writable registers that store port B data. Bits PB16DR, PB5DR, and PB3DR to PB1DR correspond to pins PB16, PB5, and PB3 to PB1, respectively (multiplexed functions omitted here) in the SH7125.
Page 579 Section 16 I/O Ports • PBDRH (SH7124) Bit: Initial value: R/W: Initial Bit Name Value Description 15 to 0 — All 0 Reserved These bits are always read as 0. The write value should always be 0. • PBDRL (SH7125) Bit: Initial value: R/W:...
Page 580 Section 16 I/O Ports • PBDRL (SH7124) Bit: Initial value: R/W: Initial Bit Name Value Description 15 to 6 — All 0 Reserved These bits are always read as 0. The write value should always be 0. PB5DR See table 16.4. —...
Page 581: Port B Port Registers H And L (Pbprh And Pbprl)
Section 16 I/O Ports 16.2.3 Port B Port Registers H and L (PBPRH and PBPRL) PBPRH and PBPRL are 16-bit read-only registers that always return the states of the pins regardless of the PFC setting. Bits PB16PR, PB5PR, and PB3PR to PB1PR correspond to pins PB16, PB5, and PB3 to PB31, respectively (multiplexed functions omitted here) in the SH7125.
Page 582 Section 16 I/O Ports • PBPRL (SH7125) Bit: Initial value: R/W: Initial Bit Name Value Description  15 to 6 All 0 Reserved These bits are always read as 0. The write value should always be 0. PB5PR Pin state R The pin state is returned regardless of the PFC setting.
Page 583 Section 16 I/O Ports • PBPRL (SH7124) Bit: Initial value: R/W: Initial Bit Name Value Description  15 to 6 All 0 Reserved These bits are always read as 0. The write value should always be 0. PB5PR Pin state R The pin state is returned regardless of the PFC setting.
Page 584: Port E
Section 16 I/O Ports 16.3 Port E Port E in the SH7125 is an input/output port with the 16 pins shown in figure 16.5. PE15 (I/O)/ TIOC4D (I/O)/ IRQOUT (output) PE14 (I/O)/ TIOC4C (I/O) PE13 (I/O)/ TIOC4B (I/O)/ MRES (input) PE12 (I/O)/ TIOC4A (I/O) PE11 (I/O)/ TIOC3D (I/O) PE10 (I/O)/ TIOC3C (I/O)
Page 585 Section 16 I/O Ports Port E in the SH7124 is an input/output port with the 12 pins shown in figure 16.6. PE15 (I/O)/ TIOC4D (I/O)/ IRQOUT (output) PE14 (I/O)/ TIOC4C (I/O) PE13 (I/O)/ TIOC4B (I/O)/ MRES (input) PE12 (I/O)/ TIOC4A (I/O) PE11 (I/O)/ TIOC3D (I/O) PE10 (I/O)/ TIOC3C (I/O) Port E...
Page 586: Register Descriptions
Section 16 I/O Ports 16.3.1 Register Descriptions Port E is a 16-bit input/output port in the SH7125 and a 12-bit input/output port in the SH7124. Port E has the following registers. For details on register addresses and register states during each processing, refer to section 20, List of Registers.
Page 587 Section 16 I/O Ports • PEDRL (SH7125) Bit: PE15 PE14 PE13 PE12 PE11 PE10 Initial value: R/W: Initial Bit Name Value Description PE15DR See table 16.6. PE14DR PE13DR PE12DR PE11DR PE10DR PE9DR PE8DR PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR Rev.
Page 588 Section 16 I/O Ports • PEDRL (SH7124) Bit: PE15 PE14 PE13 PE12 PE11 PE10 Initial value: R/W: Initial Bit Name Value Description PE15DR See table 16.6. PE14DR PE13DR PE12DR PE11DR PE10DR PE9DR PE8DR  7 to 4 All 0 Reserved These bits are always read as 0.
Page 589: Port E Port Register L (Peprl)
Section 16 I/O Ports 16.3.3 Port E Port Register L (PEPRL) PEPRL is a 16-bit read-only register that always returns the states of the pins regardless of the PFC setting. Bits PE15PR to PE0PR correspond to pins PE15 to PE0 (multiplexed functions omitted here) in the SH7125.
Page 590 Section 16 I/O Ports • PEPRL (SH7124) Bit: PE15 PE14 PE13 PE12 PE11 PE10 Initial value: R/W: Initial Bit Name Value Description PE15PR Pin state R The pin state is returned regardless of the PFC setting. These bits cannot be modified. PE14PR Pin state R PE13PR...
Page 591: Port F
Section 16 I/O Ports 16.4 Port F Port F in the SH7125 and SH7124 is an input-only port with the eight pins shown in figure 16.7. PF7 (input)/AN7 (input) PF6 (input)/AN6 (input) PF5 (input)/AN5 (input) PF4 (input)/AN4 (input) Port F PF3 (input)/AN3 (input) PF2 (input)/AN2 (input) PF1 (input)/AN1 (input)
Page 592: Port F Data Register L (Pfdrl)
Section 16 I/O Ports 16.4.2 Port F Data Register L (PFDRL) The port F data register L (PFDRL) is a 16-bit read-only register that stores port F data. Bits PF7DR to PF0DR correspond to pins PF7 to PF0 (multiplexed functions omitted here) in the SH7125 and SH7124.
Page 593: Section 17 Flash Memory
Section 17 Flash Memory Section 17 Flash Memory This LSI has 128-Kbyte, 64-Kbyte, or 32-Kbyte on-chip flash memory. The flash memory has the following features. 17.1 Features • Capacitance SH71253, SH71243: 128 Kbytes SH71252, SH71242: 64 Kbytes SH71241: 32 Kbytes •...
Page 594 Section 17 Flash Memory • Programming/erasing time The flash memory programming time is t ms (Typ.) in 128-byte simultaneous programming and t /128 ms per byte. The erasing time is t s (Typ.) per block. • Number of programming The number of flash memory programming can be up to N times.
Page 595: Overview
Section 17 Flash Memory 17.2 Overview 17.2.1 Block Diagram Internal address bus Internal data bus (32 bits) FCCS FPCS Memory MAT unit Control unit FECS User MAT: 128 kbytes 64 kbytes FKEY 32 kbytes FTDAR Flash memory FWE pin Operating Mode pins mode [Legend]...
Page 596: Operating Mode
Section 17 Flash Memory 17.2.2 Operating Mode When each mode pin and the FWE pin are set in the reset state and the reset signal is released, the microcomputer enters each operating mode as shown in figure 17.2. For the setting of each mode pin and the FWE pin, see tables 17.1 to 17.4.
Page 597: Mode Comparison
Section 17 Flash Memory 17.2.3 Mode Comparison The comparison table of programming and erasing related items about boot mode and user program mode is shown in table 17.2. Table 17.2 Comparison of Programming Modes Programming/erasing On-Board Programming Off-Board environment Programming Boot Mode User Program Mode* Programming/...
Page 598: Flash Memory Configuration
Section 17 Flash Memory 17.2.4 Flash Memory Configuration This LSI's flash memory is configured by the 128-Kbyte, 64-Kbyte, or 32-Kbyte user MAT. • 128KB <User MAT> SH71253 Address H'00000000 SH71243 • 64KB SH71252 SH71242 • 32KB 128 kbytes, 64 kbytes, SH71241 Address H'00007FFF or 32 kbytes...
Page 599: Programming/Erasing Interface
Section 17 Flash Memory 17.2.6 Programming/Erasing Interface Programming/erasing is executed by downloading the on-chip program to the on-chip RAM and specifying the program address/data and erase block by using the interface registers/parameters. The procedure program is made by the user in user program mode. The overview of the procedure is as follows.
Page 600 Section 17 Flash Memory (2) Download of On-Chip Program The on-chip program is automatically downloaded by clearing VBR of the CPU to H'84000000 and then setting the SCO bit in the flash code control and status register (FCCS) and the flash key code register (FKEY), which are programming/erasing interface registers. The user MAT is replaced to the embedded program storage area when downloading.
Page 601: Input/Output Pins
Section 17 Flash Memory 17.3 Input/Output Pins Flash memory is controlled by the pins as shown in table 17.3. Table 17.3 Pin Configuration Pin Name Symbol Function Power-on reset Input Reset Flash programming Input Hardware protection when enable programming flash memory Mode 1 Input Sets operating mode of this LSI...
Page 602 Section 17 Flash Memory Table 17.4 (1) Register Configuration Initial Access Register Name Abbreviation* Value Address Size Flash code control and status FCCS R, W* H'00* H'FFFFCC00 register H'80* Flash program code select register FPCS H'00 H'FFFFCC01 Flash erase code select register FECS H'00 H'FFFFCC02...
Page 603 Section 17 Flash Memory Table 17.5 Register/Parameter and Target Mode Initiali- Program- Download zation ming Erasure Read √ Programming/ FCCS — — — — erasing interface √ FPCS — — — — registers √ PECS — — — — √ √...
Page 604: Programming/Erasing Interface Registers
Section 17 Flash Memory 17.4.2 Programming/Erasing Interface Registers The programming/erasing interface registers are as described below. They are all 8-bit registers that can be accessed in bytes. (1) Flash Code Control and Status Register (FCCS) FCCS is configured by bits which request the monitor of the FWE pin state and error occurrence during programming or erasing flash memory and the download of the on-chip program.
Page 605 Section 17 Flash Memory Initial Value Bit Name Description FLER Flash Memory Error Indicates an error occurs during programming and erasing flash memory. When FLER is set to 1, flash memory enters the error protection state. When FLER is set to 1, high voltage is applied to the internal flash memory.
Page 606 Section 17 Flash Memory Initial Value Bit Name Description (R)/W Source Program Copy Operation Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS/FECS is automatically downloaded in the on-chip RAM area specified by FTDAR.
Page 607 Section 17 Flash Memory (2) Flash Program Code Select Register (FPCS) FPCS selects the on-chip programming program to be downloaded. Bit: PPVS Initial value: R/W: Initial Bit Name Value Description  7 to 1 All 0 Reserved These bits are always read as 0. The write value should always be 0.
Page 608 Section 17 Flash Memory Initial Value Bit Name Description EPVB Erase Pulse Verify Block Selects the erasing program. 0: On-chip erasing program is not selected [Clearing condition] When transfer is completed 1: On-chip erasing program is selected (4) Flash Key Code Register (FKEY) FKEY is a register for software protection that enables download of the on-chip program and programming/erasing of flash memory.
Page 609 Section 17 Flash Memory (5) Flash Transfer Destination Address Register (FTDAR) FTDAR specifies the on-chip RAM address to which the on-chip program is downloaded. Make settings for FTDAR before writing 1 to the SCO bit in FCCS. The initial value is H'00 which points to the start address (H'FFFFA000) in on-chip RAM.
Page 610: Programming/Erasing Interface Parameters
Section 17 Flash Memory 17.4.3 Programming/Erasing Interface Parameters The programming/erasing interface parameters specify the operating frequency, user branch destination address, storage place for program data, programming destination address, and erase block and exchanges the processing result for the downloaded on-chip program. This parameter uses the general registers of the CPU (R4, R5, and R0) or the on-chip RAM area.
Page 611 Section 17 Flash Memory Table 17.6 Usable Parameters and Target Modes Pro- Name of Abbrevia- Down- Initiali- gram- Initial Parameter tion load zation ming Erasure R/W Value Allocation √ Download pass/fail DPFR — — — Undefined On-chip result RAM* √ √...
Page 612 Section 17 Flash Memory Bit: Initial value: R/W: Initial Bit Name Value Description  7 to 3 Undefined R/W Unused Return 0. Undefined R/W Source Select Error Detect The on-chip program which can be downloaded can be specified as only one type. When more than two types of the program are selected, the program is not selected, or the program is selected without mapping, an error occurs.
Page 613 Section 17 Flash Memory (2) Programming/Erasing Initialization The on-chip programming/erasing program to be downloaded includes the initialization program. The specified period pulse must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. The operating frequency of the CPU must be set.
Page 614 Section 17 Flash Memory Initial Value Bit Name Description  31 to Undefined R/W Unused Return 0. 15 to 0 F15 to F0 Undefined R/W Frequency Set Set the operating frequency of the CPU. The setting value must be calculated as the following methods. 1.
Page 615 Section 17 Flash Memory Initial Value Bit Name Description 31 to 0 UA31 to Undefined R/W User Branch Destination Address When the user branch is not required, address 0 (H'84000000) must be set. The user branch destination must be an area other than the flash memory, an area other than the RAM area in which on-chip program has been transferred, or the external bus space.
Page 616 Section 17 Flash Memory (2.3) Flash pass/fail result parameter (FPFR: general register R0 of CPU) This parameter indicates the return value of the initialization result. Bit: Initial value: R/W: Bit: Initial value: R/W: Initial Bit Name Value Description 31 to 3  Undefined R/W Unused Return 0.
Page 617 Section 17 Flash Memory (3) Programming Execution When flash memory is programmed, the programming destination address and programming data on the user MAT must be passed to the programming program in which the program data is downloaded. 1. The start address of the programming destination on the user MAT is set in general register R5 of the CPU.
Page 618 Section 17 Flash Memory Initial Value Bit Name Description 31 to 0 MOA31 to Undefined R/W MOA31 to MOA0 MOA0 Store the start address of the programming destination on the user MAT. The consecutive 128-byte programming is executed starting from the specified start address of the user MAT.
Page 619 Section 17 Flash Memory (3.3) Flash pass/fail parameter (FPFR: general register R0 of CPU) This parameter indicates the return value of the program processing result. Bit: Initial value: R/W: Bit: Initial value: R/W: Initial Bit Name Value Description 31 to 7  Undefined R/W Unused Return 0.
Page 620 Section 17 Flash Memory Initial Value Bit Name Description Undefined R/W Programming Execution Error Detect 1 is returned to this bit when the specified data could not be written because the user MAT was not erased or when flash-memory related register settings are partially changed on returning from the user branch processing.
Page 621 Section 17 Flash Memory Initial Value Bit Name Description Undefined R/W Success/Fail Indicates whether the program processing has ended normally or not. 0: Programming has ended normally (no error) 1: Programming has ended abnormally (error occurs) (4) Erasure Execution When flash memory is erased, the erase-block number on the user MAT must be passed to the erasing program which is downloaded.
Page 622 Section 17 Flash Memory Initial Value Bit Name Description 31 to 8  Undefined R/W Unused Return 0. • 7 to 0 EBS[7:0] Undefined R/W 128-kbyte flash memory Set the erase-block number in the range from 0 to 9. 0 corresponds to the EB0 block and 9 corresponds to the EB9 block.
Page 623 Section 17 Flash Memory Initial Value Bit Name Description Undefined R/W Erasure Mode Related Setting Error Detect Returns the check result of whether the signal input to the FWE pin is high and whether the error protection state is not entered. When a low-level signal is input to the FWE pin or the error protection state is entered, 1 is written to this bit.
Page 624 Section 17 Flash Memory Initial Value Bit Name Description  2, 1 Undefined R/W Unused Return 0. Undefined R/W Success/Fail Indicates whether the erasing processing has ended normally or not. 0: Erasure has ended normally (no error) 1: Erasure has ended abnormally (error occurs) Rev.
Page 625: On-Board Programming Mode
Section 17 Flash Memory 17.5 On-Board Programming Mode When the pin is set in on-board programming mode and the reset start is executed, the on-board programming state that can program/erase the on-chip flash memory is entered. On-board programming mode has two operating modes: user program mode and boot mode. For details on the pin setting for entering each mode, see table 17.1.
Page 626 Section 17 Flash Memory (1) SCI Interface Setting by Host When boot mode is initiated, this LSI measures the low period of asynchronous SCI- communication data (H'00), which is transmitted consecutively by the host. The SCI transmit/receive format is set to 8-bit data, 1 stop bit, and no parity. This LSI calculates the bit rate of transmission by the host by means of the measured low period and transmits the bit adjustment end sign (1 byte of H'00) to the host.
Page 627 Section 17 Flash Memory (2) State Transition Diagram Figure 17.8 gives an overview of the state transitions after the chip has been started up in boot mode. For details on boot mode, see section 17.8.1, Specifications of the Standard Serial Communications Interface in Boot Mode.
Page 628 Section 17 Flash Memory (Bit rate matching) Reception of H'00, …, H'00 Start in boot mode Bit rate matching (reset in boot mode) Reception of inquiry/selection command Execute processing Wait for inquiry/selection in response to inquiry/ command Response to selection command inquiry/selection command Erasure of entire user MAT and...
Page 629: User Program Mode (Only In On-Chip 128-Kbyte And 64-Kbyte Rom Version)
Section 17 Flash Memory 17.5.2 User Program Mode (Only in On-Chip 128-Kbyte and 64-Kbyte ROM Version) The user MAT can be programmed/erased in user program mode. Programming/erasing is executed by downloading the program in the microcomputer. The overview flow is shown in figure 17.9. High voltage is applied to internal flash memory during the programming/erasing processing.
Page 630 Section 17 Flash Memory (1) On-Chip RAM Address Map when Programming/Erasing is Executed Parts of the procedure program that are made by the user, like download request, programming/erasing procedure, and decision of the result, must be executed in the on-chip RAM.
Page 631 Section 17 Flash Memory (2) Programming Procedure in User Program Mode The procedures for download, initialization, and programming are shown in figure 17.11. Start programming procedure program Select on-chip program to be downloaded and set download destination (2.9) (2.1) Set FKEY to H'5A by FTDAR Set FKEY to H'A5 Set parameter to R4 and...
Page 632 Section 17 Flash Memory 128-byte programming is performed in one program processing. When more than 128-byte programming is performed, programming destination address/program data parameter is updated in 128-byte units and programming is repeated. When less than 128-byte programming is performed, data must total 128 bytes by adding the invalid data.
Page 633 Section 17 Flash Memory • After the on-chip program storage area is returned to the user MAT space, execution returns to the user procedure program. After download is completed and the user procedure program is running, the VBR setting can be changed.
Page 634 Section 17 Flash Memory • The start address in the user branch destination is set to the FUBRA parameter (general register R5). When the user branch processing is not required, 0 must be set to FUBRA. When the user branch is executed, the branch destination is executed in flash memory other than the one that is to be programmed.
Page 635 Section 17 Flash Memory parameter FPFR. Since the unit is 128 bytes, the lower eight bits (MOA7 to MOA0) must be in the 128-byte boundary of H'00 or H'80. • FMPDR setting If the storage destination of the program data is flash memory, even when the program execution routine is executed, programming is not executed and an error is returned to the FPFR parameter.
Page 636 Section 17 Flash Memory (3) Erasing Procedure in User Program Mode The procedures for download, initialization, and erasing are shown in figure 17.12. Start erasing procedure program Select on-chip program to be downloaded and set download destination Set FKEY to H'5A by FTDAR (3.1) Set FKEY to H'A5...
Page 637 Section 17 Flash Memory A single divided block is erased by one erasing processing. For block divisions, see figure 17.4. To erase two or more blocks, update the erase block number and perform the erasing processing for each block. (3.1) Select the on-chip program to be downloaded Set the EPVB bit in FECS to 1.
Page 638: Protection
Section 17 Flash Memory 17.6 Protection There are three kinds of flash memory program/erase protection: hardware, software, and error protection. 17.6.1 Hardware Protection Programming and erasing of flash memory is forcibly disabled or suspended by hardware protection. In this state, the downloading of an on-chip program and initialization of the flash memory are possible.
Page 639: Software Protection
Section 17 Flash Memory 17.6.2 Software Protection Software protection is set up in any of two ways: by disabling the downloading of on-chip programs for programming and erasing and by means of a key code. Table 17.9 Software Protection Function to be Protected Programming/ Item Description...
Page 640 Section 17 Flash Memory Note that the reset signal should only be released after providing a reset input over a period longer than the normal 100 µs. Since high voltages are applied during programming/erasing of the flash memory, some voltage may still remain even after the error protection state has been entered. For this reason, it is necessary to reduce the risk of damage to the flash memory by extending the reset period so that the charge is released.
Page 641: Usage Notes
Section 17 Flash Memory 17.7 Usage Notes 17.7.1 Interrupts during Programming/Erasing (1) Download of On-Chip Program (1.1) VBR setting change Before downloading the on-chip program, VBR must be set to H'84000000. If VBR is set to a value other than H'84000000, the interrupt vector table is placed in the user MAT on setting H'84000000 to VBR.
Page 642 Section 17 Flash Memory (2) Interrupts during programming/erasing Though an interrupt processing can be executed at realtime during programming/erasing of the downloaded on-chip program, the following limitations and notes are applied. 1. When flash memory is being programmed or erased, the user MAT cannot be accessed. Prepare the interrupt vector table and interrupt processing routine in on-chip RAM.
Page 643: Other Notes
Section 17 Flash Memory 17.7.2 Other Notes 1. Download Time of On-Chip Program The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 3 Kbytes or less. Accordingly, when the CPU clock frequency is 20 MHz, the download for each program takes approximately 10 ms at maximum.
Page 644 Section 17 Flash Memory 4. Compatibility with Programming/Erasing Program of Conventional F-ZTAT SH Microcomputer A programming/erasing program for flash memory used in the conventional F-ZTAT SH microcomputer which does not support download of the on-chip program by a SCO transfer request cannot run in this LSI.
Page 645: Supplementary Information
Section 17 Flash Memory 17.8 Supplementary Information 17.8.1 Specifications of the Standard Serial Communications Interface in Boot Mode The boot program activated in boot mode communicates with the host via the on-chip SCI of the LSI. The specifications of the serial communications interface between the host and the boot program are described below.
Page 646 Section 17 Flash Memory Reset Bit rate matching state Bit rate matching Inquiry-and-selection state Wait for inquiry and selection Inquiry Selection Inquiry Selection processing processing Enter programming/erasure state Programming/erasure state Erase user MAT Wait for programming/erasure selection Programming Erasure Programming Erasure Checking processing...
Page 647 Section 17 Flash Memory Host Boot program H'00 (max. 30 times) Measures the length of one bit H'00 (bit rate matching complete) H'55 H'E6 (response) H'FF (error) Figure 17.16 Sequence of Bit-Rate Matching • Communications protocol Formats in the communications protocol between the host and boot program after completion of the bit-rate matching are as follows.
Page 648 Section 17 Flash Memory One-character command Command or response or one-character response n-character command Data or n-character response Size Checksum Command or response Error response Error code Error response 128-byte Address Data (n bytes) programming command Command Checksum Response to Data size Data memory read command...
Page 649 Section 17 Flash Memory • Inquiry-and-Selection State In this state, the boot program returns information on the flash ROM in response to inquiry commands sent from the host, and selects the device, clock mode, and bit rate in response to the respective selection commands.
Page 650 Section 17 Flash Memory All commands in the above table, except for the boot program state inquiry command (H'4F), are valid until the boot program accepts the transition-to-programming/erasure state command (H'40). That is, until the transition command is accepted, the host can continue to send commands listed in the above table until it has made the necessary inquiries and selections.
Page 651 Section 17 Flash Memory Device selection In response to the device selection command, the boot program sets the specified device as the selected device. The boot program will return the information on the selected device in response to subsequent inquiries. Command H'10 Size...
Page 652 Section 17 Flash Memory  Response H'31 (1 byte): Response to the inquiry on clock modes  Size (1 byte): The total length of the number of modes and mode data fields.  Mode (1 byte): Selectable clock mode (example: H'01 denotes clock mode 1) ...
Page 653 Section 17 Flash Memory Inquiry on frequency multipliers In response to the inquiry on frequency multipliers, the boot program returns information on the settable frequency multipliers or divisors. Command H'22  Command H'22 (1 byte): Inquiry on frequency multipliers Response H'32 Size No.
Page 654 Section 17 Flash Memory Inquiry on operating frequency In response to the inquiry on operating frequency, the boot program returns the number of operating frequencies and the maximum and minimum values. Command H'23  Command H'23 (1 byte): Inquiry on operating frequency Response H'33 Size...
Page 655 Section 17 Flash Memory Inquiry on user MATs In response to the inquiry on user MATs, the boot program returns the number of user MAT areas and their addresses. Command H'25  Command H'25 (1 byte): Inquiry on user MAT information Response H'35 Size...
Page 656 Section 17 Flash Memory  Response H'36 (1 byte): Response to the inquiry on erasure blocks  Size (2 bytes): The total length of the number of blocks and first and last address fields.  Number of blocks (1 byte): The number of erasure blocks in flash memory ...
Page 657 Section 17 Flash Memory  Command H'3F (1 byte): New bit rate selection  Size (1 byte): The total length of the bit rate, input frequency, number of multipliers, and multiplier fields  Bit rate (2 bytes): New bit rate The bit rate value divided by 100 should be set here (for example, to select 19200 bps, the set H'00C0, which is 192 in decimal notation).
Page 658 Section 17 Flash Memory H'26: Frequency multiplier error (the specified multiplier does not match an available one). H'27: Operating frequency error (the specified operating frequency is not within the range from the minimum to the maximum value). The received data are checked in the following ways. 1.
Page 659 Section 17 Flash Memory When the new bit rate is selectable, the boot program returns an ACK code to the host and then makes the register setting to select the new bit rate. The host then sends an ACK code at the new bit rate, and the boot program responds to this with another ACK code, this time at the new bit rate.
Page 660 Section 17 Flash Memory (11) Transition to the programming/erasure state In response to the transition to the programming/erasure state command, the boot program transfers the erasing program and runs it to erase any data in the user MAT. On completion of this erasure, the boot program returns the ACK code and enters the programming/erasure state.
Page 661 Section 17 Flash Memory • Command Error Command errors are generated by undefined commands, commands sent in an incorrect order, and the inability to accept a command. For example, sending the clock-mode selection command before device selection or an inquiry command after the transition-to-programming/erasure state command generates a command error.
Page 662 Section 17 Flash Memory • Programming/Erasure State In this state, the boot program must select the form of programming corresponding to the programming-selection command and then write data in response to 128-byte programming commands, or perform erasure in block units in response to the erasure-selection and block- erasure commands.
Page 663 Section 17 Flash Memory The sequence of programming by programming-selection and 128-byte programming commands is shown in figure 17.19. Host Boot program Programming selection (H'42, H'43) Transfer the program that performs programming 128-byte programming (address and data) Programming Repeat 128-byte programming (H'FFFFFFFF) Figure 17.19 Sequence of Programming Selection of user MAT programming In response to the command for selecting programming of the user MAT, the boot program...
Page 664 Section 17 Flash Memory  ERROR (1 byte): Error code H'54: Error in selection processing (processing was not completed because of a transfer error) 128-byte programming In response to the 128-byte programming command, the boot program executes the flash-writing program transferred in response to the command to program into the user MAT. Command H'50 Address for programming...
Page 665 Section 17 Flash Memory The specified address should be on a boundary corresponding to the unit of programming (programming size). For example, when programming 128 bytes of data, the lowest byte of the address should be either H'00 or H'80. When less than 128 bytes of data are to be programmed, the host should transmit the data after padding the vacant bytes with H'FF.
Page 666 Section 17 Flash Memory • Erasure Erasure is performed by issuing the erasure selection command and then one or more block erasure commands. Firstly, the host sends the erasure selection command to select erasure; after that, it sends a block erasure command to actually erase a specific block.
Page 667 Section 17 Flash Memory Select erasure In response to the erasure selection command, the boot program transfers the program that performs erasure, i.e. erases data in the user MAT. Command H'48  Command H'48 (1 byte): Selects erasure. Response H'06 ...
Page 668 Section 17 Flash Memory Error response H'D8 ERROR  Error response H'D8 (1 byte): Error response to the block erasure command  ERROR (1 byte): Error code H'11: Sum-check error H'29: Block number error (the specified block number is incorrect.) H'51: Erasure error (an error occurred during erasure.) On receiving the command with H'FF as the block number, the boot program stops erasure processing and waits for the next programming/erasure selection command.
Page 669 Section 17 Flash Memory  Area (1 byte): H'01: User MAT An incorrect area specification will produce an address error.  Address where reading starts (4 bytes)  Amount to read (4 bytes): The amount of data to be read ...
Page 670 Section 17 Flash Memory • Sum checking of the user MAT In response to the command for sum checking of the user MAT, the boot program adds all bytes of data in the user MAT and returns the result. Command H'4B ...
Page 671 Section 17 Flash Memory • Inquiry on boot program state In response to the command for inquiry on the state of the boot program, the boot program returns an indicator of its current state and error information. This inquiry can be made in the inquiry-and- selection state or the programming/erasure state.
Page 672: Areas For Storage Of The Procedural Program And Data For Programming
Section 17 Flash Memory Table 17.15 Error Codes Code Description H'00 No error H'11 Sum check error H'21 Non-matching device code error H'22 Non-matching clock mode error H'24 Bit-rate selection failure H'25 Input frequency error H'26 Frequency multiplier error H'27 Operating frequency error H'29 Block number error...
Page 673 Section 17 Flash Memory table, interrupt processing routine, and user branch program should be transferred to on-chip RAM before programming/erasing of the flash memory starts. 5. The flash memory is not accessible during programming/erasing operations. Therefore, the programming/erasing program must be downloaded to on-chip RAM in advance. Areas for executing each procedure program for initiating programming/erasing, the user program at the user branch destination for programming/erasing, the interrupt vector table, and the interrupt processing routine must be located in on-chip RAM.
Page 674 Section 17 Flash Memory Table 17.17 (1) Usable Area for Programming in User Program Mode Storable/Executable Area Selected MAT Embedded Program On-Chip User User Storage Item √ Program data storage area — — √ √ √ Selecting on-chip program to be downloaded √...
Page 675 Section 17 Flash Memory Table 17.17 (2) Usable Area for Erasure in User Program Mode Storable/Executable Area Selected MAT Embedded Program On-Chip User User Storage Item √ √ √ Selecting on-chip program to be downloaded √ √ √ Writing H'A5 to key register √...
Page 676: Off-Board Programming Mode
Off-Board Programming Mode A PROM programmer can be used to perform programming/erasing via a socket adapter, just as for a discrete flash memory. Use a PROM programmer that supports the Renesas 128-Kbyte flash memory on-chip MCU device type (F-ZTAT128DV5). Rev. 3.00 Sep. 27, 2007 Page 656 of 758...
Page 677: Section 18 Ram
Section 18 RAM Section 18 RAM This LSI has an on-chip high-speed static RAM. The on-chip RAM is connected to the CPU by a 32-bit data bus (L bus), enabling 8, 16, or 32-bit width access to data in the on-chip RAM. The on-chip RAM is allocated to different addresses according to each product as shown in figure 18.1.
Page 678: Usage Notes
Section 18 RAM 18.1 Usage Notes 18.1.1 Module Standby Mode Setting RAM can be enabled/disabled by the standby control register. The initial value enables RAM operation. RAM access is disabled by setting the module standby mode. For details, see section 19, Power-Down Modes.
Page 679: Section 19 Power-Down Modes
Section 19 Power-Down Modes Section 19 Power-Down Modes This LSI supports the following power-down modes: sleep mode, software standby mode, and module standby mode. 19.1 Features • Supports sleep mode, software standby mode, and module standby mode. 19.1.1 Types of Power-Down Modes This LSI has the following power-down modes.
Page 680 Section 19 Power-Down Modes Table 19.1 States of Power-Down Modes State On-Chip On-Chip Peripheral Mode Transition Method CPG CPU Register Memory Modules Canceling Procedure • Sleep Execute SLEEP Runs Halts Held Runs Reset instruction with STBY bit in STBCR1 cleared to 0. •...
Page 681: Input/Output Pins
Section 19 Power-Down Modes 19.2 Input/Output Pins Table 19.2 lists the pins used for the power-down modes. Table 19.2 Pin Configuration Pin Name Abbr. Description Power-on reset Input Power-on reset input signal. Power-on reset by low level. MRES Manual reset Input Manual reset input signal.
Page 682: Standby Control Register 1 (Stbcr1)
Section 19 Power-Down Modes 19.3.1 Standby Control Register 1 (STBCR1) STBCR1 is an 8-bit readable/writable register that specifies the state of the power-down mode. Bit: STBY Initial value: R/W: Initial Value Bit Name Description STBY Standby Specifies transition to software standby mode. 0: Executing SLEEP instruction makes this LSI sleep mode 1: Executing SLEEP instruction makes this LSI...
Page 683: Standby Control Register 2 (Stbcr2)
Section 19 Power-Down Modes 19.3.2 Standby Control Register 2 (STBCR2) STBCR2 is an 8-bit readable/writable register that controls the RAM operation in power-down mode. Bit: MSTP Initial value: R/W: Initial Value Bit Name Description MSTP7 Module Stop Bit 7 When this bit is set to 1, the supply of the clock to the RAM is halted.
Page 684: Standby Control Register 3 (Stbcr3)
Section 19 Power-Down Modes 19.3.3 Standby Control Register 3 (STBCR3) STBCR3 is an 8-bit readable/writable register that controls the operation of modules in power- down mode. Bit: MSTP MSTP MSTP Initial value: R/W: Initial Value Bit Name Description  7, 6 All 1 Reserved These bits are always read as 1.
Page 685: Standby Control Register 4 (Stbcr4)
Section 19 Power-Down Modes 19.3.4 Standby Control Register 4 (STBCR4) STBCR4 is an 8-bit readable/writable register that controls the operation of modules in power- down mode. Bit: MSTP MSTP MSTP MSTP Initial value: R/W: Initial Value Bit Name Description  Reserved This bit is always read as 1.
Page 686: Standby Control Register 5 (Stbcr5)
Section 19 Power-Down Modes Initial Value Bit Name Description MSTP16 Module Stop Bit 16 When this bit is set to 1, the supply of the clock to the A/D_0 is halted. 0: A/D_0 operates 1: Clock supply to A/D_0 halted 19.3.5 Standby Control Register 5 (STBCR5) STBCR5 is an 8-bit readable/writable register that controls the operation of modules in power-...
Page 687: Standby Control Register 6 (Stbcr6)
Section 19 Power-Down Modes 19.3.6 Standby Control Register 6 (STBCR6) STBCR6 is an 8-bit readable/writable register that specifies the state of the power-down modes. Bit: STBY Initial value: R/W: Initial Value Bit Name Description UBCRST UBC Software Reset Resetting the PC trace unit of UBC is controlled by software.
Page 688: Ram Control Register (Ramcr)
Section 19 Power-Down Modes 19.3.7 RAM Control Register (RAMCR) RAMCR is an 8-bit readable/writable register that enables/disables the access to the on-chip RAM. Bit: RAME Initial value: R/W: Initial Value Bit Name Description  7 to 5 All 0 Reserved These bits are always read as 0.
Page 689: Sleep Mode
Section 19 Power-Down Modes 19.4 Sleep Mode 19.4.1 Transition to Sleep Mode Executing the SLEEP instruction when the STBY bit in STBCR1 is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged.
Page 690: Software Standby Mode
Section 19 Power-Down Modes 19.5 Software Standby Mode 19.5.1 Transition to Software Standby Mode This LSI switches from a program execution state to software standby mode by executing the SLEEP instruction when the STBY bit in STBCR1 and the STBYMD bit in STBCR6 are set to 1. In software standby mode, not only the CPU but also the clock and on-chip peripheral modules halt.
Page 691: Canceling Software Standby Mode
Section 19 Power-Down Modes 19.5.2 Canceling Software Standby Mode Software standby mode is canceled by interrupts (NMI, IRQ) or a reset. Canceling with Interrupt The WDT can be used for hot starts. When an NMI or IRQ interrupt (edge detection) is detected, the clock will be supplied to the entire LSI and software standby mode will be canceled after the time set in the timer control/status register of the WDT has elapsed.
Page 692: Module Standby Mode
Section 19 Power-Down Modes 19.6 Module Standby Mode 19.6.1 Transition to Module Standby Mode Setting the MSTP bits in the standby control registers (STBCR2 to STBCR5) to 1 halts the supply of clocks to the corresponding on-chip peripheral modules. This function can be used to reduce the power consumption in normal mode.
Page 693: Section 20 List Of Registers
Section 20 List of Registers Section 20 List of Registers This section gives information on internal I/O registers. The contents of this section are as follows: 1. Register Address Table (in the order from a lower address) • Registers are listed in the order from lower allocated addresses. •...
Page 694: Register Address Table (In The Order From Lower Addresses)
Section 20 List of Registers 20.1 Register Address Table (In the Order from Lower Addresses) Access sizes are indicated with the number of bits. Access states are indicated with the number of specified reference clock states. These values are those at 8-bit access (B), 16-bit access (W), or 32-bit access (L).
Page 695 Section 20 List of Registers Number of Number of Access Register Name Abbreviation Bits Address Module Access Size States Timer control register_3 TCR_3 H'FFFFC200 MTU2 8, 16, 32 MPφ reference Timer control register_4 TCR_4 H'FFFFC201 B: 2, W: 2, L: 4 Timer mode register_3 TMDR_3 H'FFFFC202...
Page 696 Section 20 List of Registers Number of Number of Access Register Name Abbreviation Bits Address Module Access Size States Timer interrupt skipping counter TITCNT H'FFFFC231 MTU2 MPφ reference Timer buffer transfer set register TBTER H'FFFFC232 B: 2, W: 2, L: 4 Timer dead time enable register TDER H'FFFFC234...
Page 697 Section 20 List of Registers Number of Number of Access Register Name Abbreviation Bits Address Module Access Size States Timer general register C_0 TGRC_0 H'FFFFC30C MTU2 16, 32 MPφ reference Timer general register D_0 TGRD_0 H'FFFFC30E B: 2, W: 2, L: 4 Timer general register E_0 TGRE_0 H'FFFFC320...
Page 698 Section 20 List of Registers Number of Number of Access Register Name Abbreviation Bits Address Module Access Size States Timer control register V_5 TCRV_5 H'FFFFC494 MTU2 MPφ reference Timer I/O control register V_5 TIORV_5 H'FFFFC496 B: 2, W: 2, L: 4 Timer counter W_5 TCNTW_5 H'FFFFC4A0...
Page 699 Section 20 List of Registers Number of Number of Access Register Name Abbreviation Bits Address Module Access Size States Compare match timer start register CMSTR H'FFFFCE00 8, 16, 32 Pφ reference Compare match timer control/status CMCSR_0 H'FFFFCE02 8, 16 B: 2, W: 2, L: 4 register_0 Compare match counter_0 CMCNT_0...
Page 700 Section 20 List of Registers Number of Number of Access Register Name Abbreviation Bits Address Module Access Size States Port E I/O register L PEIORL H'FFFFD306 8, 16 Pφ reference Port E control register L4 PECRL4 H'FFFFD310 8, 16, 32 B: 2, W: 2, L: 4 Port E control register L3 PECRL3...
Page 701 Section 20 List of Registers Number of Number of Access Register Name Abbreviation Bits Address Module Access Size States Interrupt priority register D IPRD H'FFFFE982 INTC Pφ reference Interrupt priority register E IPRE H'FFFFE984 B: 2, W: 2 Interrupt priority register F IPRF H'FFFFE986 Interrupt priority register H...
Page 702: Register Bit List
Section 20 List of Registers 20.2 Register Bit List Addresses and bit names of each on-chip peripheral module are shown below. As for 16-bit or 32-bit registers, they are shown in two or four rows. Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2...
Page 703 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module TCR_3 CCLR[2:0] CKEG[1:0] TPSC[2:0] MTU2 TCR_4 CCLR[2:0] CKEG[1:0] TPSC[2:0]   TMDR_3 MD[3:0]   TMDR_4 MD[3:0] TIORH_3 IOB[3:0] IOA[3:0] TIORL_3 IOD[3:0] IOC[3:0] TIORH_4 IOB[3:0] IOA[3:0] TIORL_4...
Page 704 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module TCNTS MTU2 TCBR TGRC_3 TGRD_3 TGRC_4 TGRD_4   TSR_3 TCFD TCFV TGFD TGFC TGFB TGFA   TSR_4 TCFD TCFV TGFD TGFC TGFB TGFA TITCR T3AEN...
Page 705 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module       TWCR MTU2    TSTR CST4 CST3 CST2 CST1 CST0    TSYR SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 ...
Page 706 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module    TIER_1 TTGE TCIEU TCIEV TGIEB TGIEA MTU2    TSR_1 TCFD TCFU TCFV TGFB TGFA TCNT_1 TGRA_1 TGRB_1   ...
Page 707 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module    TIORV_5 IOC[4:0] MTU2 TCNTW_5 TGRW_5       TCRW_5 TPSC[1:0]    TIORW_5 IOC[4:0]    ...
Page 708 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module    ADCSR_1 ADIE TRGE CONADF A/D (Channel 1) CKSL[1:0] ADM[1:0] ADCS CH[2:0]        ADCR_1 ADST  ...
Page 709 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module     POECR1 MTU2PE0ZE POE MTU2PE3ZE MTU2PE2ZE MTU2PE1ZE      POECR2 MTU2P1CZE MTU2P2CZE MTU2P3CZE      ...
Page 710 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module         PBDRH (SH7125)        PB16DR       ...
Page 711 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module         PBPRH (SH7125)        PB16PR       ...
Page 712 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module         IFCR       IRQMD1 IRQMD0        ...
Page 713 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module IPRD MTU2_0 MTU2_0 MTU2_0 MTU2_0 MTU2_0 MTU2_0 MTU2_0 MTU2_0 INTC MTU2_1 MTU2_1 MTU2_1 MTU2_1 MTU2_1 MTU2_1 MTU2_1 MTU2_1 IPRE MTU2_2 MTU2_2 MTU2_2 MTU2_2 MTU2_2 MTU2_2 MTU2_2 MTU2_2...
Page 714 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module BDRA BDA31 BDA30 BDA29 BDA28 BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16 BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 BDA9 BDA8 BDA7 BDA6...
Page 715 Section 20 List of Registers Register Abbreviation 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0 Module    BRSR BSA27 BSA26 BSA25 BSA24 BSA23 BSA22 BSA21 BSA20 BSA19 BSA18 BSA17 BSA16 BSA15 BSA14 BSA13 BSA12 BSA11 BSA10 BSA9 BSA8 BSA7 BSA6 BSA5...
Page 716: Register States In Each Operating Mode
Section 20 List of Registers 20.3 Register States in Each Operating Mode Register Software Module Abbreviation Standby Standby Power-on reset Manual reset Sleep Module SCSMR_0 Initialized Retained Initialized Initialized Retained (Channel 0) SCBRR_0 Initialized Retained Initialized Initialized Retained SCSCR_0 Initialized Retained Initialized Initialized...
Page 717 Section 20 List of Registers Register Software Module Abbreviation Power-on reset Manual reset Standby Standby Sleep Module TIORL_3 Initialized Retained Initialized Initialized Retained MTU2 TIORH_4 Initialized Retained Initialized Initialized Retained TIORL_4 Initialized Retained Initialized Initialized Retained TIER_3 Initialized Retained Initialized Initialized Retained TIER_4...
Page 718 Section 20 List of Registers Register Software Module Abbreviation Power-on reset Manual reset Standby Standby Sleep Module TBTM_4 Initialized Retained Initialized Initialized Retained MTU2 TADCR Initialized Retained Initialized Initialized Retained TADCORA_4 Initialized Retained Initialized Initialized Retained TADCORB_4 Initialized Retained Initialized Initialized Retained TADCOBRA_4...
Page 719 Section 20 List of Registers Register Software Module Abbreviation Power-on reset Manual reset Standby Standby Sleep Module TSR_1 Initialized Retained Initialized Initialized Retained MTU2 TCNT_1 Initialized Retained Initialized Initialized Retained TGRA_1 Initialized Retained Initialized Initialized Retained TGRB_1 Initialized Retained Initialized Initialized Retained TICCR...
Page 720 Section 20 List of Registers Register Software Module Abbreviation Power-on reset Manual reset Standby Standby Sleep Module ADDR0 Initialized Retained Initialized Initialized Retained A/D (Channel 0) ADDR1 Initialized Retained Initialized Initialized Retained ADDR2 Initialized Retained Initialized Initialized Retained ADDR3 Initialized Retained Initialized Initialized...
Page 721 Section 20 List of Registers Register Software Module Abbreviation Power-on reset Manual reset Standby Standby Sleep Module  PADRL Initialized Retained Retained Retained  PAIORL Initialized Retained Retained Retained  PACRL4 Initialized Retained Retained Retained  PACRL3 Initialized Retained Retained Retained ...
Page 722 Section 20 List of Registers Register Software Module Abbreviation Power-on reset Manual reset Standby Standby Sleep Module  STBCR5 Initialized Retained Retained Retained Power-down modes  STBCR6 Initialized Retained Retained Retained  WTCNT Initialized* Retained Retained Retained  WTCSR Initialized* Retained Retained Retained...
Page 723 Section 20 List of Registers Register Software Module Abbreviation Power-on reset Manual reset Standby Standby Sleep Module BDRB Initialized Retained Retained Initialized Retained BDMRB Initialized Retained Retained Initialized Retained BRCR Initialized Retained Retained Initialized Retained BRSR Initialized Retained Retained Initialized Retained BRDR Initialized...
Page 724 Section 20 List of Registers Rev. 3.00 Sep. 27, 2007 Page 704 of 758 REJ09B0243-0300...
Page 725: Section 21 Electrical Characteristics
Section 21 Electrical Characteristics Section 21 Electrical Characteristics All values for electrical characteristics are preliminary, and are subject to change without notice as a result of characteristics evaluation. 21.1 Absolute Maximum Ratings Table 21.1 lists the absolute maximum ratings. Table 21.1 Absolute Maximum Ratings Item Symbol Value...
Page 726: Dc Characteristics
Section 21 Electrical Characteristics 21.2 DC Characteristics Tables 21.2 and 21.3 list DC characteristics. Table 21.2 DC Characteristics Conditions: V = AV = 4.0 V to 5.5 V, V = PLLV = AV = 0 V, = –20 to +85°C (consumer specifications), = –40 to +85°C (industrial specifications) Test Item...
Page 727 Section 21 Electrical Characteristics Test Item Symbol Min. Typ. Max. Unit Conditions − 0.8   Output high PE9, PE11 to PE15 = –5 mA voltage WDTOVF − 0.5   = –100 µA − 0.5   All other output pins = –200 µA −...
Page 728 Section 21 Electrical Characteristics Table 21.3 Permitted Output Current Values Conditions: V = AV = 4.0 V to 5.5 V, V = PLLV = AV = 0 V, = –20 to +85°C (consumer specifications), = –40 to +85°C (industrial specifications) Item Symbol Min.
Page 729: Ac Characteristics
Section 21 Electrical Characteristics 21.3 AC Characteristics Signals input to this LSI are basically handled as signals in synchronization with a clock. The setup and hold times for input pins must be followed. Table 21.4 Maximum Operating Frequency Conditions: V = AV = 4.0 V to 5.5 V, V = PLLV...
Page 730: Clock Timing
Section 21 Electrical Characteristics 21.3.1 Clock Timing Table 21.5 Clock Timing Conditions: V = AV = 4.0 V to 5.5 V, V = PLLV = AV = 0 V, = –20 to +85°C (consumer specifications), = –40 to +85°C (industrial specifications) Reference Item Symbol...
Page 731 Section 21 Electrical Characteristics Oscillation stabilized internal clock (Min.) RESW RESS OSC1 Note: Oscillation stabilization time when the on-chip oscillator is in use. Figure 21.2 Power-On Oscillation Stabilization Time Standby period Oscillation stabilized internal clock RESW MRESW OSC2 RES, MRES Note: Oscillation stabilization time when the on-chip oscillator is in use.
Page 732: Control Signal Timing
Section 21 Electrical Characteristics 21.3.2 Control Signal Timing Table 21.6 Control Signal Timing Conditions: V = AV = 4.0 V to 5.5 V, V = PLLV = AV = 0 V, = –20 to +85°C (consumer specifications), = –40 to +85°C (industrial specifications) Item Symbol Min.
Page 733 Section 21 Electrical Characteristics RESS RESS RESW MD1, FWE MRESS MRESS MRES MRESW Figure 21.5 Reset Input Timing RESH RESS MRESH MRESS MRES NMIH NMIS IRQH IRQS IRQ3 to IRQ0 Figure 21.6 Interrupt Signal Input Timing Rev. 3.00 Sep. 27, 2007 Page 713 of 758 REJ09B0243-0300...
Page 734 Section 21 Electrical Characteristics IRQOD IRQOD IRQOUT Figure 21.7 Interrupt Signal Output Timing Rev. 3.00 Sep. 27, 2007 Page 714 of 758 REJ09B0243-0300...
Page 735: Multi Function Timer Pulse Unit 2 (Mtu2) Timing
Section 21 Electrical Characteristics 21.3.3 Multi Function Timer Pulse Unit 2 (MTU2) Timing Table 21.7 Multi Function Timer Pulse Unit 2 (MTU2) Timing Conditions: V = AV = 4.0 V to 5.5 V, V = PLLV = AV = 0 V, = –20 to +85°C (consumer specifications), = –40 to +85°C (industrial specifications) Reference...
Page 736 Section 21 Electrical Characteristics TCKS TCKS TCLKA to TCLKD TCKWL TCKWH Figure 21.9 MTU2 Clock Input Timing Rev. 3.00 Sep. 27, 2007 Page 716 of 758 REJ09B0243-0300...
Page 737: I/O Port Timing
Section 21 Electrical Characteristics 21.3.4 I/O Port Timing Table 21.8 I/O Port Timing Conditions: V = AV = 4.0 V to 5.5 V, V = PLLV = AV = 0 V, = –20 to +85°C (consumer specifications), = –40 to +85°C (industrial specifications) Reference Item Symbol...
Page 738: Watchdog Timer (Wdt) Timing
Section 21 Electrical Characteristics 21.3.5 Watchdog Timer (WDT) Timing Table 21.9 Watchdog Timer (WDT) Timing Conditions: V = AV = 4.0 V to 5.5 V, V = PLLV = AV = 0 V, = –20 to +85°C (consumer specifications), = –40 to +85°C (industrial specifications) Reference Item Symbol...
Page 739: Serial Communication Interface (Sci) Timing
Section 21 Electrical Characteristics 21.3.6 Serial Communication Interface (SCI) Timing Table 21.10 Serial Communication Interface (SCI) Timing Conditions: V = AV = 4.0 V to 5.5 V, V = PLLV = AV = 0 V, = –20 to +85°C (consumer specifications), = –40 to +85°C (industrial specifications) Reference Figure...
Page 740 Section 21 Electrical Characteristics scyc SCK0 to SCK2 (input/output) TXD0 to TXD2 (transmit data) RXD0 to RXD2 (receive data) SCI input/output timing (clock synchronous mode) TXD0 to TXD2 (transmit data) RXD0 to RXD2 (receive data) SCI input/output timing (asynchronous mode) Figure 21.13 SCI Input/Output Timing Rev.
Page 741: Port Output Enable (Poe) Timing
Section 21 Electrical Characteristics 21.3.7 Port Output Enable (POE) Timing Table 21.11 Port Output Enable (POE) Timing Conditions: V = AV = 4.0 V to 5.5 V, V = PLLV = AV = 0 V, = –20 to +85°C (consumer specifications), = –40 to +85°C (industrial specifications) Reference Item...
Page 742: A/D Converter Timing
Section 21 Electrical Characteristics 21.3.8 A/D Converter Timing Table 21.12 A/D Converter Timing Conditions: V = AV = 4.0 V to 5.5 V, V = PLLV = AV = 0 V, = –20 to +85°C (consumer specifications), = –40 to +85°C (industrial specifications) Reference Item Symbol...
Page 743: Conditions For Testing Ac Characteristics
Section 21 Electrical Characteristics 21.3.9 Conditions for Testing AC Characteristics • Input signal level: V (Max.)/V (Min.) • Output signal reference level: 2.0 V (high level), 0.8 V (low level) DUT output LSI output pin Notes: is the total value that includes the capacitance of the measurement instrument and is set as follows for the respective pins.
Page 744: A/D Converter Characteristics
Section 21 Electrical Characteristics 21.4 A/D Converter Characteristics Table 21.13 A/D Converter Characteristics Conditions: V = AV = 4.0 V to 5.5 V, V = PLLV = AV = 0 V, = –20 to +85°C (consumer specifications), = –40 to +85°C (industrial specifications) Item Min.
Page 745: Flash Memory Characteristics
Section 21 Electrical Characteristics 21.5 Flash Memory Characteristics Table 21.14 Flash Memory Characteristics Conditions: V = AV = 4.0 V to 5.5 V, V = PLLV = AV = 0 V, = –20 to +85°C (consumer specifications), = –40 to +85°C (industrial specifications) Item Symbol Min.
Page 746: Usage Note
Section 21 Electrical Characteristics 21.6 Usage Note 21.6.1 Notes on Connecting V Capacitor This LSI includes an internal step-down circuit to automatically reduce the internal power supply voltage to an appropriate level. Between this internal stepped-down power supply (V pin) and pin, a capacitor (ranging from 0.1 to 0.47 µF) for stabilizing the internal voltage needs to the V be connected.
Page 747: Appendix
Appendix Appendix Pin States Pin initial states differ according to MCU operating modes. See section 15, Pin Function Controller (PFC), for details. Table A.1 Pin States (SH7125) Pin Function Pin State Reset State Power-Down State Oscillation POE Function Software Type Pin Name Stop Detected Used...
Page 748 Appendix Pin Function Pin State Reset State Power-Down State Oscillation POE Function Software Type Pin Name Stop Detected Used Power-On Manual Standby Sleep SCK0 to SCK2 RXD0 to RXD2 TXD0 to TXD2 A/D Converter AN0 to AN7 ADTRG I/O Ports PA0 to PA15 PB1 to PB3, PB5, PB16...
Page 749 Appendix Table A.2 Pin States (SH7124) Pin Function Pin State Reset State Power-Down State Oscillation POE Function Software Type Pin Name Stop Detected Used Power-On Manual Standby Sleep Clock XTAL EXTAL System control MRES WDTOVF Operating mode control ASEMD0 Interrupt IRQ1 to IRQ3 IRQOUT MTU2...
Page 750 Appendix Pin Function Pin State Reset State Power-Down State Oscillation POE Function Software Type Pin Name Stop Detected Used Power-On Manual Standby Sleep I/O Ports PA0, PA1, PA3, PA4, PA6 to PA9 PB1, PB3, PB5 PE0 to PE3 PE8, PE10 PE9, PE11 to PE15 PF0 to PF7 [Legend]...
Page 751: Product Code Lineup
Appendix Product Code Lineup Package (Package Code) Product Type Product Code SH7125 Flash memory version Consumer product R5F71253N50FP LQFP-64 (FP-64K) (on-chip 128-kbyte) Industrial product R5F71253D50FP Consumer product R5F71253N50FA QFP-64 (FP-64H) Industrial product R5F71253D50FA Consumer product R5F71253N50NP VQFN-64 (TNP-64BV) Industrial product R5F71253D50NP Flash memory version Consumer product...
Page 752: Package Dimensions
Appendix Package Dimensions Figure C.1 LQFP-64 Rev. 3.00 Sep. 27, 2007 Page 732 of 758 REJ09B0243-0300...
Page 753 Appendix Figure C.2 QFP-64 Rev. 3.00 Sep. 27, 2007 Page 733 of 758 REJ09B0243-0300...
Page 754 Appendix Figure C.3 LQFP-48 Rev. 3.00 Sep. 27, 2007 Page 734 of 758 REJ09B0243-0300...
Page 755 Appendix Figure C.4 VQFN-64 Rev. 3.00 Sep. 27, 2007 Page 735 of 758 REJ09B0243-0300...
Page 756 Appendix Figure C.5 VQFN-52 Rev. 3.00 Sep. 27, 2007 Page 736 of 758 REJ09B0243-0300...
Page 757: Main Revisions And Additions In This Edition
Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details) – – Added VQFN-64 and VQFN-52 specifications Descriptions of on-chip 32-kbyte flash memory for SH7124 Table 1.1 Features Deleted Items Specification • Multi-function Pulse output modes timer pulse unit 2 One shot, toggle, PWM, (MTU2)
Page 758 Item Page Revision (See Manual for Details) 4.4.1 Frequency Control Register Added/Deleted (FRQCR) Before making changes to FRQCR, set the module stop bit in the standby control register 2, 3, 4, 5, and 6 to 1 and stop clock supply to each module except the CPU, on-chip ROM, and on-chip-RAM.
Page 759 Item Page Revision (See Manual for Details) Table 5.5 Reset Status Added Conditions for Transition to Reset State Internal State On-Chip Peripheral POE, PFC, Type overflow MRES CPU, INTC Module I/O Port Power- High Overflow High Initialized Initialized Initailzed reset Manual High Initialized Not...
Page 760 Item Page Revision (See Manual for Details) 8.4 Access to on-chip Peripheral Added I/O Register The L bus access takes one Iclk cycle, I bus access takes one Bclk cycle, and peripheral bus access takes two Pclk cycles. When the on-chip peripheral I/O register is accessed by the CPU, the period required for preparation for data transfer to the I bus is a period of 3 Iclk cycles.
Page 761 Item Page Revision (See Manual for Details) Figure 8.3 Timing of Read Access Added to the Peripheral Bus Iclk (Iclk:Bclk:Pclk = 4:2:1) L bus Bclk I bus Pclk Peripheral bus Table 9.28 TIORU_5, TIORV_5, Amended and TIORW_5 (Channel 5) Description Bit 4 TGRU_5, TGRV_5, and TIC5U, TIC5V, and TIC5W Pin...
Page 762 Item Page Revision (See Manual for Details) Figure 9.41 Example of Operation Amended without Dead Time Compare register TGRA_4 Data1 Data2 Output waveform Initial output Output waveform Initial output Output waveform is active-low. Figure 9.71 Example of Operation Changed when Buffer Transfer is Linked with Interrupt Skipping (BTE1 = 1 and BTE0 = 0) Figure 9.78 Example of External...
Page 763 Item Page Revision (See Manual for Details) Figure 10.5 Pin State when a Added Power-On Reset is Issued from Pφ the Watchdog Timer POE input Timer Pin state Timer output General input output High impedance state 1Pφ cycle PFC setting value Timer output General input Power-on reset by WDT...
Page 764 Item Page Revision (See Manual for Details) 12.3.8 Serial Port Register Amended (SCSPTR) Bit Bit Name Initial R/W Description Value SPB1DT Undefined R/W Clock Port Data in Serial Port Specifies the data output through the SCK pin in the serial port. Output should be enabled by the SPB1IO bit (for details, refer to the SPB1IO bit description).
Page 765 Item Page Revision (See Manual for Details) 12.4.3 Clock Synchronous Mode Added (Channel 1 in the SH7124 is not When only reception is performed, the synchronous Available) clock continues to be output until an overrun error occurs or the RE bit is cleared to 0. For the reception of n characters, select the external clock as the clock source.
Page 766 Item Page Revision (See Manual for Details) 13.4.3 Single-Cycle Scan Mode Deleted In 2-channel scan mode, since the channels are divided into group 0 and group 1, even though group 0 is operating in single-cycle scan mode, the contents of the A/D data registers for group 1 are retained.
Page 767 Item Page Revision (See Manual for Details) Figure 13.4 Example of 2-Channel Added Scanning TGRA_3 TADCORA_4 TCNT_4 TADCORB_4 H'0000 A/D conversion start request conversion conversion conversion conversion A/D conversion end (ADF) CONADF bit in ADCSR = 1 CONADF bit in ADCSR = 0 13.6 Definitions of A/D Conversion Amended Accuracy...
Page 768 Item Page Revision (See Manual for Details) 17.1 Features Amended This mode uses the dedicated socket adapter and PROM programmer. 17.1 Features Amended The operating frequency at programming/erasing is a maximum of 40 MHz (Pφ). 17.2.3 Mode Comparison Amended The comparison table of programming and erasing related items about boot mode, and user program mode, and programmer mode is shown in table 17.2.
Page 769 A PROM programmer can be used to perform programming/erasing via a socket adapter, just as for a discrete flash memory. Use a PROM programmer that supports the Renesas 128-Kbyte flash memory on-chip MCU device type (F-ZTAT128DV5). 18.1.3 Initial Values in RAM...
Page 770 Item Page Revision (See Manual for Details) 19.4.2 Canceling Sleep Mode Added Do not cancel sleep mode with an interrupt. 19.7.2 Executing the SLEEP Added Instruction Apply either of the following measures before executing the SLEEP instruction to initiate the transition to sleep mode or software standby mode.
Page 771 Item Page Revision (See Manual for Details) Figure 21.10 I/O Port Input/Output Timing PRWH/L Port (read) Port (write) Table 21.10 Serial Amended Communication Interface (SCI) Item Min. Timing  Transmit data delay time Clock synchronous Receive data setup time + 50 pcyc Receive data hold time + 50...
Page 772 Rev. 3.00 Sep. 27, 2007 Page 752 of 758 REJ09B0243-0300...
Page 773: Index
Index Clock synchronous mode ....411, 454 Clock timing ........... 710 A/D conversion time....... 491 CMT interrupt sources ......507 A/D converter (ADC) ......475 Compare match timer (CMT) ....501 A/D converter activation......319 Complementary PWM mode ....269 A/D converter characteristics....
Page 774 General illegal instructions ....... 82 Manual reset..........76 General registers ........19 MCU operating modes......49 Global-base register (GBR) ...... 20 Module standby mode......672 Module standby mode setting......474, 498, 508, 658 MTU2 functions........152 MTU2 interrupts ........317 Hardware protection .......
Page 775 PC trace ..........138 BRCR..........127 Peripheral clock (Pφ) ........ 55 BRDR..........133 Permissible signal source impedance..498 BRSR ..........132 Pin function controller (PFC) ....511 CMCNT ..........505 Pin states of this LSI in each CMCOR ..........505 processing state........
Page 776 PBDRL ..........558 TCBR..........229 PBIORH ..........531 TCDR..........228 PBIORL..........531 TCNT ..........209 PBPRH ..........561 TCNTCMPCLR........188 PBPRL..........561 TCNTS..........227 PECRL1..........537 TCR............. 162 PECRL2..........537 TCSYSTR........... 214 PECRL3..........537 TDDR ..........228 PECRL4..........537 TDER..........234 PEDRL ..........
Page 777 SCSPTR and SCI pins ......470 The address map for the operating Sending a break signal ......472 modes ............51 Sequential break ........137 Trap instructions ........81 Serial communication interface (SCI) ..411 Shift instructions........42 Single chip mode ........50 Single mode ..........
Page 778 Rev. 3.00 Sep. 27, 2007 Page 758 of 758 REJ09B0243-0300...
Page 779 Publication Date: Rev.1.00, Mar. 25, 2005 Rev.3.00, Sep. 27, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.  2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Page 780 Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan http://www.renesas.com RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Page 782 SH7125 Group, SH7124 Group Hardware Manual...

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