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Addressing
Interrupt processing
There must be a precise response to an interrupt in OB 2 once the interrupt has been enabled.
This block is called by the module with the PRAL-N
duced as follows:
The interrupt flag is "1" if an interrupt is present, irrespective of the type of pulse edge generating
the interrupt.
Every interrupt request is stored until the interrupt is serviced. The module reports the request via
the internal bus system of the CPU (PRAL-N signal).
This produces the following chronological sequence:
Subunit A
Interrupt request
PRAL-N
Synchronization of
interrupt processing
Call OB 2
with LPY, LPW
Evaluation of the inputs
Figure 5-11. Chronological Sequence of Interrupt Processing
Every input enabled for the interrupt must be scanned in OB 2. The address of the inputs is
obtained by incrementing the initial module address by one.
Example: Scanning inputs 0 and 1 of the module with the initial address 8 for an interrupt.
STL
L
PY
T
IB
A
I
JC
PY
A
I
JC
PY
BE
1 Negation of the PRAL signal
5-14
Subunit B
Interrupt request
PRAL-N
Synchronization of
interrupt processing
Call OB 2
with LPY, LPW
Evaluation of the inputs
9
Interrupt register is read.
9
The information is transferred to the PII.
9.0
Scan input 0.
1
Process interrupt 0 in PB 1.
9.1
Scan input 1.
2
Process interrupt 1 in PB 2.
1
signal (process interrupt). This signal is pro-
Response time of the
Meaning
S5-115F Manual
6ES5 434-7LA12
interrupt module
(typ. 1 ms)
Response time
of the
CPU
EWA 4NEB 811 6148-02
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