Bias Voltages And Laser Drive Timing - Epson EPL-5500 Service Manual

Operating Principles

2.1.2.6 Bias Voltages and Laser Drive Timing

Figure 2-20 is a diagram of the drum charge bias voltage, image transfer bias voltage, and the
developing bias voltage control circuit. These bias voltages are generated from the +24 VDC from
the high-voltage supply board (PWB-F). If the printer detects a case-open condition, the interlock
switch is set to off, which cuts the +24 VDC, which, in turn, cuts the bias voltages.
These bias voltages are controlled by the main board (C169 MAIN-B). The HV-T signal is the
image transfer bias voltage control. While this signal is LOW, the image transfer electrode comb is
charged to from +3 to +6K VDC by the high-voltage supply circuit. HV SEL1 and HV SEL2 are
image transfer bias level control signals.
The HVB signal is the digital signal for developing bias voltage control. This signal controls the bias
on/off. The BIAS MON signal controls the bias voltage level (–300 V to –375K VDC) using pulse
data. The image density is controlled by the developing bias voltage level.
Power Supply
Board
(PWB-E)
+24 VDC
Interlock
SW
Figure 2-20. High-Voltage Supply Block Diagram
2-14
Main
Board
(C169 MAIN-B)
PWB-S
+24 VDC
HV-C
HV-T
HV SEL1
HV SEL2
HV B
BIAS MON
EPL-5500 Service Manual
High Voltage Supply
Board
(PWB-F)
Drum Charge
-2.0 K VDC
Image Transfer
Bias
3K to 6 K VDC
Developing
Bias
-270 to -370 VDC
Doctor Toner Blade
Bias -500 VDC
Seal Bias
-250 VDC
Rev. B