Interrupt Control; Dram Management - Epson EPL-5500 Service Manual

EPL-5500 Service Manual

2.2.1.3 Interrupt Control

The ASIC E05A93 determines the priority level of the interrupt and outputs it to terminals IRL0 -
IRL3. Then an interrupt is sent to the CPU. When the IRL0-3 value is 1111b, the CPU process is a
non-maskable interrupt process. When the IRL0-3 value is 0000b, the CPU process is a standard
process. When the IRL0-3 is any other value, the CPU process is a maskable interrupt process.

2.2.1.4 DRAM Management

The video controller uses DRAMs for the system RAM and for the V-RAM. In this printer, a standard
two 512K × 16 DRAMs are mounted in locations IC17 and IC18, providing a total of 1MB. CN2
SIMM sockets are provided for optional SIMM memory modules. These SIMM sockets can use 1, 2,
4, 8, 16, and 32 MB SIMMs (32-bit bus).
The DRAMs (including optional SIMMs) are managed by the ASIC E05A91. E05A91 outputs
MA0-10 (memory address), RAS/CAS, and WE signals.
RAS1,2
RAS0
DWE
E05A91
(IC2)
CAS0,1,2,3
MA0-10
CPU DATA BUS
Rev. B
DRAM
(IC17)
DRAM
(IC18)
Figure 2-30. DRAM Management
Operating Principles
SIMM
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