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IDT Tsi572 Hardware Manual

Serial rapidio switch
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IDT
Tsi572
Serial RapidIO Switch
Hardware Manual
May 18, 2012

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Summary of Contents for IDT Tsi572

  • Page 1 Titl Tsi572   Serial RapidIO Switch Hardware Manual May 18, 2012...
  • Page 2 IDT does not assume responsibility for use of any circuitry described herein other than the circuitry embodied in an IDT product. Disclosure of the information herein does not convey a license or any other right, by implication or otherwise, in any patent, trademark, or other intellectual property right of IDT. IDT products may contain errata which can affect product performance to a minor or immaterial degree.

  • Page 3: Table Of Contents

    Part Numbering Information ........... . 87 Integrated Device Technology Tsi572 Hardware Manual www.idt.com...
  • Page 4 Tsi572 Hardware Manual Integrated Device Technology May 18, 2012 www.idt.com...
  • Page 5 About this Document This section discusses general document information about the Tsi572. The following topics are described: • “Scope” on page 5 • “Document Conventions” on page 5 • “Revision History” on page 6 Scope The Tsi572 Hardware Manual discusses electrical, physical, and board layout information for the Tsi572.
  • Page 6 August 2009, Formal This is the current release of the Serial RapidIO Switch. There have been no technical changes to the document; the formatting has been updated to reflect IDT. June 2009, Formal Changes have been implemented throughout the document.
  • Page 7 The changes to this documents includes adding industrial variants of the device to “Ordering Information” on page June 2008, Advance This was the first version of the Serial RapidIO Switch. Integrated Device Technology Tsi572 Hardware Manual www.idt.com May 18, 2012...
  • Page 8 Serial RapidIO Switch Integrated Device Technology May 18, 2012 www.idt.com...

  • Page 9: Signals And Package

    “Signals” on page 10 • “Package Characteristics” on page 24 • “Thermal Characteristics” on page 27 Pinlist The pinlist and ballmap information for the Tsi572 are available by visiting www.idt.com. For more information, see the following documents: • Tsi572 Pinlist • Tsi572 Ballmap...

  • Page 10: Signals

    1x Mode: 2,3,4,5 Interrupt INT_b SP{2,4}_PWRDN SP{3,5}_PWRDN S_CLK_[p,n] TX_SWAP Ref Clks 4x Mode Lane Swap P_CLK RX_SWAP Port SP_IO_SPEED[1:0] Configuration Ports{0,2,4,6} SP_VDD SP_VDD VDD_IO VDD_IO REF_AVDD REF_AVDD Ports{0,2,4,6} SP_AVDD SP_AVDD Tsi572 Hardware Manual Integrated Device Technology May 18, 2012 www.idt.com...
  • Page 11 Definition Input Output Input/Output Open Drain SRIO Differential driver/receiver defined by RapidIO Interconnect Specification (Revision 1.3) Pulled Up internal to the Tsi572 Pulled Down internal to the Tsi572 LVTTL CMOS I/O with LVTTL thresholds Hyst Hysteresis Core Power Core supply...
  • Page 12 Serial Port 1 (SP1) Serial Port 2 (SP2) Serial Port 3 (SP3) Serial Port 4 (SP4) Serial Port 5 (SP5) Serial Port 6 (SP6) 1x or 4x Serial Port 7 (SP7) Tsi572 Hardware Manual Integrated Device Technology May 18, 2012 www.idt.com...
  • Page 13 Port n Lane D Differential Non-inverting Transmit No termination required. Data output (4x mode) SP[0,6]__TD_ O, SRIO Port n Lane D Differential Inverting Transmit Data No termination required. output (4x mode) Integrated Device Technology Tsi572 Hardware Manual www.idt.com May 18, 2012...
  • Page 14 DC blocking capacitor of Data input(4x mode) 0.1uF in series SP[0,6]_RD_n I, SRIO Port n Lane D Differential Inverting Receive Data DC blocking capacitor of input (4x mode) 0.1uF in series Tsi572 Hardware Manual Integrated Device Technology May 18, 2012 www.idt.com...
  • Page 15 1 = Port n Powered Down. Port n+1 Powered Down. Override SP{n}_PWRDN using PWDN_x1 field in “SRIO MAC x Clock Selection Register” in the Tsi572 User Manual. Output capability of this pin is only used in test mode. Must remain stable for 10 P_CLK cycles after HW_RST_B is de-asserted in order to be sampled correctly.
  • Page 16 Output capability of this pin is only used in test mode. Must remain stable for 10 P_CLK cycles after HW_RST_B is de-asserted in order to be sampled correctly. This signal is ignored after reset. Tsi572 Hardware Manual Integrated Device Technology May 18, 2012 www.idt.com...
  • Page 17 Pin must be tied off LVTTL, according to the required configuration. Either a 10K pull-up to VDD_IO or a 10K pull-down to VSS_IO. Internal pull-up may be used for logic 1. Integrated Device Technology Tsi572 Hardware Manual www.idt.com May 18, 2012...
  • Page 18 This clock is used for the register bus clock. No termination required. LVTTL The nominal frequency of this input clock is 100 MHz. For more information on programming the P_CLK operating frequency, refer to “P_CLK Programming” on page Tsi572 Hardware Manual Integrated Device Technology May 18, 2012 www.idt.com...
  • Page 19 Schmidt-triggered hard reset. Asynchronous Connect to a power-up active low reset for the entire device. reset source. LVTTL, Hyst, The Tsi572 does not contain a voltage detector to Refer to “Reset generate internal reset. Requirements” on page 64 Interrupts INT_b...
  • Page 20 If self-reset is selected, this pin remains asserted until the self reset is complete. If the Tsi572 is reset from the HARD_RST_b pin, this pin is de-asserted and remains de-asserted after HARD_RST_b is released.
  • Page 21 I2C_DISABLE I, LVTTL, Disable I C register loading after reset. When No termination required. asserted, the Tsi572 does not attempt to load Pull up to VDD_IO through register values from I a 10K resistor if I loading is not required.
  • Page 22 I2C_SEL I, CMOS, C Pin Select. Together with the I2C_SA[1,0] No termination required. pins, Tsi572 will determine the lower 2 bits of the Internal pull-up may be 7-bit address of the EEPROM address it boots used for logic 1. from.
  • Page 23 1.2V supply for CDR, Tx/Rx, and digital logic for Refer to ““Decoupling all RapidIO ports Requirements” on page 57” a. Signals for unused serial ports do not require termination and can be left as N/Cs. Integrated Device Technology Tsi572 Hardware Manual www.idt.com May 18, 2012...

  • Page 24: Package Characteristics

    Package Characteristics The Tsi572’s package characteristics are summarized in the following table. The following figures show the top, side, and bottom views of the Tsi572 package. Table 4: Package Characteristics Feature Description Package Type Heat Slug Ball Grid Array (HSBGA)
  • Page 25 Figure 2: Package Diagram — Top View Figure 3: Package Diagram — Side View Integrated Device Technology Tsi572 Hardware Manual www.idt.com May 18, 2012...
  • Page 26 Figure 4: Package Diagram — Bottom View Tsi572 Hardware Manual Integrated Device Technology May 18, 2012 www.idt.com...

  • Page 27: Thermal Characteristics

    Failure mechanisms and failure rate of a device have an exponential dependence of the IC operating temperatures. Thus, the control of the package temperature, and by extension the Junction Temperature, is essential to ensure product reliability. The Tsi572 is specified safe for operation when the Junction Temperature is within the recommended limits.
  • Page 28 Influence of the heat dissipating components assembled on the PWB (neighboring effects) Example on Thermal Data Usage Based on the Theta data and specified conditions, the following formula can be used to derive the junction temperature (Tj) of the Tsi572 with a 0m/s airflow: • Tj = è P + Tamb.

  • Page 29: Electrical Characteristics

    Electrical Characteristics This chapter provides the electrical characteristics for the Tsi572. It includes the following information: • “Absolute Maximum Ratings” on page 29 • “Recommended Operating Conditions” on page 30 • “Power” on page 31 Absolute Maximum Ratings Operating the device beyond the listed operating conditions is not recommended. Stressing the Tsi572 beyond the Absolute Maximum Rating can cause permanent damage.

  • Page 30: Recommended Operating Conditions

    Table 8 lists the recommended operating conditions. Continued exposure of IDT's devices to the maximum limits of the specified junction temperature could affect the device reliability. Subjecting the devices to temperatures beyond the maximum/minimum limits could result in a permanent failure of the device.

  • Page 31: Power

    The following sections describe the Tsi572’s power dissipation and power sequencing. 2.3.1 Power Dissipation The Tsi572’s power dissipation values are dependent on device configuration, such as line rate, port configuration, and traffic.  The following tables show the power in both 1x and 4x mode configurations in 125 C ambient temperature, typical process and voltage conditions.
  • Page 32 SPn_AVDD supplies the analog portion of the Serial RapidIO SerDes VDD_IO supplies power for all non-Serial RapidIO I/O Total power is independent of Serial RapidIO distance travelled due to Voltage Mode Driver technology used for Serial RapidIO I/O Tsi572 Hardware Manual Integrated Device Technology May 18, 2012 www.idt.com...
  • Page 33 Power-up option pins that are controlled by a logic device, in addition to all clocks, must not be driven until all power supply rails to the Tsi572 are stable. External devices also must not be permitted to sink current from, or source current to, the device because of the risk of triggering ESD protection or causing a latch-up condition.

  • Page 34: Electrical Characteristics

    (VSS) is present between the Tsi572 and the source of the signal. For example, this situation can occur if the Tsi572 is located on an AMC card that has been inserted into an active uTCA chassis and the slot power has been left in the off state.
  • Page 35 2.4.2 SerDes Transmitter (SP{n}_TD_p/n) Table 12 lists the electrical characteristics for the SerDes transmitter in the Tsi572. Table 12: SerDes Transmitter Electrical Characteristics Symbol Parameter Unit Notes TX Single-Ended Output impedance TX Differential Output Impedance TX Output Voltage (in mV) = Z...
  • Page 36 The S_CLK differential signal may be presented to the reference clock input while the switch is in an un-powered state only if a return current path (VSS) is present between the Tsi572 and the source of the signal. For example, this situation can occur if the Tsi572 is located on an AMC...
  • Page 37 LVTTL Output Low =2mA for INT_b, SW_RST_b, Voltage and TDO pins =8mA for I2C_CLK and I2C_SD pins LVTTL Output High =2mA for INT_b, SW_RST_b, DD_IO Voltage -0.5 and TDO pins Integrated Device Technology Tsi572 Hardware Manual www.idt.com May 18, 2012...
  • Page 38 2 x I . Float delay P_CLK guaranteed by design Input Clock Frequency in_P_CLK P_CLK Input Clock -100 +100 in_STAB Frequency Stability P_CLK Input Clock in_PCLK_DC Duty Cycle P_CLK Input Jitter PCLK Tsi572 Hardware Manual Integrated Device Technology May 18, 2012 www.idt.com...
  • Page 39 Resistor pull-down ohms @Vih=2.0V 2.4.5 C Interface Table 15 lists the AC specifications for Tsi572’s I C Interface. The I2C interfaces includes balls: I2C_SCLK, I2C_SD, I2C_DISABLE, I2C_MA, I2C_SEL, I2C_SA[1:0] and I2C_SEL. Table 15: AC Specifications for I C Interface Symbol...
  • Page 40 Stop Start Stop Repeated Start 2.4.6 Boundary Scan Test Interface Timing Table 16 lists the test signal timings for Tsi572. Table 16: Boundary Scan Test Signal Timings Symbol Parameter Units Notes TCK Frequency TCK High Time • Measured at 1.5V BSCH •...

  • Page 41: Layout Guidelines

    “Reflow Profile” on page 69 Overview The successful implementation of a Tsi572 in a board design is dependent on properly routing the Serial RapidIO signals and maintaining good signal integrity with a resultant low bit error rate. The sections that follow contain information for the user on principals that will maximize the signal quality of the links.

  • Page 42: Tracking Topologies

    The symmetrical stripline construction is shown in Figure 7. This method also provides clean and equal return paths through VSS and VDD from the I/O cell of the Tsi572 to the adjacent RapidIO device. The use of broadside coupled stripline construction as shown in Figure 9 is discouraged because of its inability to maintain a constant impedance throughout the entire board signal layer.
  • Page 43 Figure 10 shows the construction of the microstrip topology. Below the figure are the design equations for calculating the impedance of the trace pair. Figure 10: Differential Microstrip Construction Integrated Device Technology Tsi572 Hardware Manual www.idt.com May 18, 2012...
  • Page 44 Do not make signal layer changes that force the return path to make a reference plane change. • Decoupling capacitors do not adequately compensate for a plane split. • Do not route over via anti-pads or socket anti-pads. Tsi572 Hardware Manual Integrated Device Technology May 18, 2012 www.idt.com...
  • Page 45 25 Ghz and a corresponding wavelength of 25 mm based on a permittivity of 4.3. Therefore, the stitching vias must not be further apart than 8 mm. Integrated Device Technology Tsi572 Hardware Manual www.idt.com May 18, 2012...
  • Page 46 Transitioning across a via that is not blind or buried leaves a stub which appears as a capacitive impedance discontinuity. The portion of the via that conducts current appears inductive while the stub that develops only an electric field will appear capacitive. Tsi572 Hardware Manual Integrated Device Technology May 18, 2012...
  • Page 47 T is the thickness of the circuit board or thickness of pre-preg. • is the diameter of the via pad. • is the diameter of the antipad.  • is the dielectric constant of the circuit board material. Integrated Device Technology Tsi572 Hardware Manual www.idt.com May 18, 2012...
  • Page 48 Figure 16: Via Construction Figure 17: Signal Across a Via Signal Signal "In" "Out" Pwr & Gnd Planes Figure 18: Signal Through a Via Signal "In" Pwr & Gnd Planes Signal "Out" Tsi572 Hardware Manual Integrated Device Technology May 18, 2012 www.idt.com...
  • Page 49 Figure 19: Signal Transitioning Across a Via Simulation Model Lvia/3 Lvia/3 Lvia/3 Rvia/3 Rvia/3 Rvia/3 Cvia/4 Cvia/4 Cvia/4 Cvia/4 Figure 20: Signal Transitioning Through a Via Simulation Model Lvia/3 Lvia/3 Lvia/3 Rvia/3 Rvia/3 Rvia/3 Cvia/4 Cvia/4 Cvia/4 Cvia/4 Integrated Device Technology Tsi572 Hardware Manual www.idt.com May 18, 2012...
  • Page 50 23. The arrival of a wave front at the receiver ahead of the wave front travelling along the serpentine route is caused by the self-coupling between the parallel sections of the transmission line (Lp). Tsi572 Hardware Manual Integrated Device Technology May 18, 2012...
  • Page 51 Inter-Symbol Interference (ISI). This coupling causes pattern dependent errors on the receptor, and can substantially increase the bit error rate of the channel. Integrated Device Technology Tsi572 Hardware Manual www.idt.com May 18, 2012...
  • Page 52 Figure 25 illustrates several options for breaking out a differential pair from the Tsi572 device. The order of preference is from A to D. Case D below has a small serpentine section used to match the inter-pair skew of the differential pair.
  • Page 53 The recommended board stack up is shown in Figure 27. This design makes provision for four stripline layers and two outer microstrip layers. Layers eight and nine are provisioned as orthogonal low speed signal routing layers. Integrated Device Technology Tsi572 Hardware Manual www.idt.com May 18, 2012...
  • Page 54 Figure 27: Recommended Board Stackup Tsi572 Hardware Manual Integrated Device Technology May 18, 2012 www.idt.com...

  • Page 55: Power Distribution

    Power Distribution The Tsi572 is a high speed device with both digital and analogue components in its design. The core logic has a high threshold of noise sensitivity within its 1.2 V operating range. However, the analogue portion of the switch is considerably more sensitive.
  • Page 56 The REF_AVDD pins provide power to the S_CLK distribution circuits in the switch. The voltage should be derived from the SP_VDD plane. One ferrite will suffice to isolate the SP_VDD from the REF_AVDD. Two decoupling capacitors should be assigned to each pin. Tsi572 Hardware Manual Integrated Device Technology May 18, 2012...

  • Page 57: Decoupling Requirements

    The components should be distributed evenly around the device in order to provide filtering and bulk energy evenly to all of the ports. Use the Tsi572 ball map (available at www.idt.com) to aid in the distribution of the capacitors. Integrated Device Technology Tsi572 Hardware Manual www.idt.com...
  • Page 58 VDD_IO (3.3V) all pins 1.2V SP_AVDD (3.3V) Kelvin connection all pins separate power supplies SP_VDD (1.2V) all pins VDD (1.2V) 191 ohms SP{n}_REXT all pins VSS (all) Tsi572 Hardware Manual Integrated Device Technology May 18, 2012 www.idt.com...
  • Page 59 50mils. The width of the breakout traces should be 20mils, or the width of the pad. Via sharing should not be used in board design with the Tsi572. Figure 32: Recommended Decoupling Capacitor Pad Designs 3.5.3...
  • Page 60 Figure 34: Decoupling Bypass Frequency Bands As the frequency changes, each part of the power distribution system responds proportionally; the low-impedance power supply responds to slow events, bulk capacitors to mid-frequency events, and so forth. Tsi572 Hardware Manual Integrated Device Technology May 18, 2012 www.idt.com...

  • Page 61: Clocking And Reset

    Clocking and Reset This section discusses the requirements of the clock and reset inputs. 3.6.1 Clock Overview The Tsi572 switch input reference clocks that are used to drive the switch’s internal clock domains. Figure 35: Tsi572 Clocking Architecture C_SCLK P_CLK...
  • Page 62 PLLs, which can cause the PLLs to modulate at the same frequency as the noise. The high-frequency noise is generally beyond the PLL bandwidth which is about 1/10th the S_CLK frequency. For more information, refer to Figure 5 on page Tsi572 Hardware Manual Integrated Device Technology May 18, 2012 www.idt.com...
  • Page 63 ) * 2] / [2 * pi * (frequency in hz)] Using this equation, an example of 312.5 MHz and a phase noise of -63dBc, would produce 0.72pS RMS jitter. 3.6.2 Clock Domains Table 19: Tsi572 Clock Domains Clock Domain Clock Source Description Internal Register Domain...
  • Page 64 3.6.3 Reset Requirements The Tsi572 requires only one reset input, HARD_RST_b. The signal provided to the device must be a monotonic 3.3V swing that de-asserts a minimum of 1mS after supply rails are stable. The signal de-assertion is used to release synchronizers based on P_CLK which control the release from reset of the internal logic.

  • Page 65: Modeling And Simulation

    Verifying the signal integrity of the board design is very important for designs using GHz signalling. IDT recommends that the designer invest in a simulation tool as an aid to a successful RapidIO design. Tools are available from companies such as Mentor Graphics (HyperLynx GHZ), Ansoft (SIwave) and SiSoft (SiAuditor).

  • Page 66: Testing And Debugging Considerations

    Nexus when purchasing the Serial RapidIO pre-processor. Table 20: 8-Channel Probe Pin Assignment Number Signal Name Number Signal Name CAp/Tx0 CBp/Rx0 CAn/Tx0 CBn/Rx0 CCp/Tx1 CDp/Rx1 CCn/Tx1 CDn/Rx1 Tsi572 Hardware Manual Integrated Device Technology May 18, 2012 www.idt.com...
  • Page 67 Table 20: 8-Channel Probe Pin Assignment Number Signal Name Number Signal Name CEp/Tx2 CFp/Rx2 CEn/Tx2 CFn/Rx2 CGp/Tx3 CHp/Rx3 CGn/Tx3 CHn/rX3 Figure 37: Analyzer Probe Pad Tracking Recommendation Integrated Device Technology Tsi572 Hardware Manual www.idt.com May 18, 2012...
  • Page 68 WITH Ø 0.053" PADS (0.433) (0.1375) (0.1375) COMPONENT KEEPOUT (NEAR SIDE ONLY) BOTH SIDES 0.708 (RETENTION HOLES) RESERVED FOR RETENTION MODULE Pin 2 ALL DIMENSIONS IN INCHES UNLESS OTHERWISE SPECIFIED Tsi572 Hardware Manual Integrated Device Technology May 18, 2012 www.idt.com...

  • Page 69: Reflow Profile

    1149.6 compliant TAP controller to aid in the production testing of the SerDes pins. The Tsi572 also has the capability to read and write all internal registers through the JTAG interface. Through this interface, users may load and modify configuration registers and look up tables without the use of RapidIO maintenance transactions or an I C EEPROM.
  • Page 70 Tsi572 Hardware Manual Integrated Device Technology May 18, 2012 www.idt.com...

  • Page 71: Clocking

    “P_CLK Programming” on page 75 Line Rate Support The Tsi572 supports all of the RapidIO Interconnect Specification (Revision 1.3) specified line rates of 1.25, 2.50, and 3.125 Gbaud. The device also supports line rates that are outside of the RapidIO specification.
  • Page 72 1. This information assumes a +/- 100 ppm clock tolerance that must be obeyed between link partners. All bit and register settings that are documented for operation with S_CLK = 156.25 .MHz also apply to the use of 153.6 MHz and 125 MHz. For more clocking information, see “Clocks” in the Tsi572 User Manual.
  • Page 73 The example EEPROM loading script in the “EEPROM Scripts” appendix of the Tsi572 User Manual configures ports six and eight of the Tsi572. Other ports can be added to the script and configured by editing the text. The script is written assuming that no other contents are required in the EEPROM.
  • Page 74 14. Set the RX_EN bit in the SMACx_CFG_CH0-3 register — Write offset 0x132B0 with 0x203CE513 — Write offset 0x132B4 with 0x203CE513 — Write offset 0x132B8 with 0x203CE513 — Write offset 0x132BC with 0x203CE513 Tsi572 Hardware Manual Integrated Device Technology May 18, 2012 www.idt.com...

  • Page 75: P_Clk Programming

    RapidIO Specifications Directly Affected by Changes in the P_CLK Frequency The following sections describe how changing the P_CLK frequency to below the recommended 100 MHz operation affect the counters and state machines in the Tsi572 that are defined in the RapidIO Interconnect Specification (Revision 1.3). A.2.1.1 Port Link Time-out CSR RapidIO Part 6: 1x/4x LP-Serial Physical Layer Specification Revision 1.3: Section...
  • Page 76 SILENCE_TIMER_EN to be deasserted. When the state machine is not in the SILENT state, SILENCE_TIMER_DONE is deasserted IDT Implementation The Tsi572’s silence timer does not have user programmable registers. The silence timer is sourced from the P_CLK and any changes to P_CLK are directly reflected in the timer timeout period. Tsi572 Hardware Manual...
  • Page 77 DISCOVERY state, DISCOVERY_TIMER_DONE is de-asserted. IDT Implementation The Tsi572’s discovery timer is programmed in the RapidIO Port x Discovery Timer. The DISCOVERY_TIMER field is used by serial ports configured to operate in 4x mode. The DISCOVERY_TIMER allows time for the link partner to enter its discovery state, and if the link partner supports 4x mode, for all four lanes to be aligned.
  • Page 78 When enabled, this timer is used to determine when a link is powered up and enabled, but dead (that is, there is no link partner responding). When a link is declared dead, the transmitting port on the Tsi572 removes all packets from its transmit queue and ensure that all new packets sent to port are dropped rather than placed in the transmit queue.
  • Page 79 • P_CLK is 10 ns • Tsi572 reset value is 0x0063 MSDIV Period Divider for Milli-Second Based Timers The MSDIV field divides the USDIV period down further for use by the Arbitration Timeout Timer, the Transaction Timeout Timer, and the Boot/Diagnostic Timeout Timer.
  • Page 80 Period (START_SETUP) = (START_SETUP * Period(PCLK)) — PCLK is 10ns — Reset time is 4.71 microseconds. — Tsi572 reset value is 0x01D7 START_HOLD Count for the START Condition Hold Period The START_HOLD field defines the minimum hold time for the START condition; that is, from I2C_SD seen low to I2C_SCLK pulled low.
  • Page 81 A value of zero results in no idle detect period, meaning the bus will be sensed as idle immediately. — Reset time is 51 microseconds — Tsi572 reset value is 0x0033 A.2.3.4 I2C_SD Setup and Hold Timing Register The I2C_SD Setup and Hold Timing Register programs the setup and hold times for the I2C_SD signal when output by either the master or slave interface.
  • Page 82 — P_CLK is 10 ns — Reset time is 5.00 microseconds (100 kHz) — Tsi572 reset value is 0x01F4 SCL_LOW Count for I2C_SCLK Low Period The SCL_LOW field defines the nominal low period of the clock, from falling edge to rising edge of I2C_SCLK.
  • Page 83 Period(SCL_MINL) = (SCL_MINL * Period(P_CLK)) — P_CLK is 10 ns — Reset time is 4.71 microseconds — Tsi572 reset value is 0x01D7 A.2.3.7 I2C_SCLK Low and Arbitration Timeout Register The I2C_SCLK Low and Arbitration Timeout Register programs the I2C_SCLK low timeout and the Arbitration timeout.
  • Page 84 — USDIV is the microsecond time defined in I2C Time Period Divider Register. — This timeout is disabled on reset, and is not used during boot load. — Tsi572 reset value is 0x0000 TRAN_TO Count for Transaction Timeout Period The TRAN_TO field defines the maximum amount of time for a transaction on the I2C bus. This covers the period from Start to Stop.
  • Page 85 — Tsi572 reset value is 0x0FA0 A.2.4 Other Performance Factors This section describes any other factors that may impact the performance of the Tsi572 if P-CLK is programmed to operate lower than the recommended 100 MHz frequency. A.2.4.1 Internal Register Bus Operation The internal register bus, where all the internal registers reside, is a synchronous bus clocked by the P_CLK source.
  • Page 86 Tsi572 Hardware Manual Integrated Device Technology May 18, 2012 www.idt.com...

  • Page 87: Ordering Information

    Ordering Information This chapter discusses ordering information and describes the part numbering system for the Tsi572. Ordering Information When ordering the Tsi572 please refer to the device by its full part number, as displayed in Table Table 25: Tsi572 Ordering Information...
  • Page 88 — Q - Plastic quad flatpack (QFP) • G – IDT products fit into three RoHS-compliance categories: — Y - RoHS Compliant (6of6) – These products contain none of the six restricted substances above the limits set in the EU Directive 2002/95/EC.
  • Page 89 CORPORATE HEADQUARTERS for SALES: for Tech Support: 6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1533 San Jose, CA 95138 www.idt.com sRIO@idt.com May 18, 2012...
  • Page 90 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: IDT (Integrated Device Technology) TSI572-10GIL TSI572-10GCL TSI572-10GILV TSI572-10GCLV...

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