Port Allocations - Icom IC-F8101 Service Manual

4-4 PORT ALLOCATIONS

• FRONT CPU (DISPLAY-A UNIT: IC6004)
Pin Line
No. Name
2 LEDC LCD dimmer control.
CPU reset.
7 RESET
L=The CPU is reset.
17 TXD L-bus communication line to the MAIN CPU.
18 RXD L-bus communication line to the MAIN CPU.
LCD driver reset.
19 LRES
L=The driver is reset.
L-bus wakeup line.
27 RXD
L=Wakeup.
[ ] input.
28 IOK
L=Pushed.
[] input.
29 P3K
L=Pushed.
[] input.
30 P2K
L=Pushed.
[] input.
31 P1K
L=Pushed.
[ –] input.
32 DNK
L=Pushed.
[ +] input.
33 UPK
L=Pushed.
[ ] input.
34 EMGK
L=Pushed.
[ ] input.
35 MENK
L=Pushed.
[ ] input.
36 CALK
L=Pushed.
LCD driver control.
41 LCS
L=Enabled.
42–49 DB0–DB7 LCD driver control. (Parallel data bus)
LCD driver control.
51 LWR
L=Data write status.
LCD driver control.
52 LA0
H=In the address select mode.
LCD driver control.
55 LRD
L=Data read status.
8V power supply line control.
56 FPWRS
H=While the transceiver's power is ON.
MIC gain control.
57 MGAIN
H=The gain increases +20 dB.
[5 JKL] input.
58 T5K
L=Pushed.
[6 MNO] input.
59 T6K
L=Pushed.
[7 PRS/CLAR] input.
60 T7K
L=Pushed.
[8 TUV/CTALK] input.
61 T8K
L=Pushed.
[1 QZ] input.
62 T1K
L=Pushed.
[2 ABC] input.
63 T2K
L=Pushed.
[3 DEF/MODE] input.
64 T3K
L=Pushed.
[4 GHI] input.
65 T4K
L=Pushed.
[ ] input.
66 TLK
L=Pushed.
[ ] input.
67 TRK
L=Pushed.
[] input.
68 CHDK
L=Pushed.
[] input.
69 CHUK
L=Pushed.
[9 WXY/TUNER] input.
70 T9K
L=Pushed.
[0 _] input.
71 T0K
L=Pushed.
[ @?/MUTE] input.
72 MUTK
L=Pushed.
Description I/O
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Pin Line
No. Name
[# A
73 SCNK
L=Pushed.
I
75 TEMP LCD temperature sensing voltage.
76 MICL MIC input level sensing voltage.
I
• MAIN CPU (MAIN-A UNIT: IC1806)
I
Pin Line
No. Name
I
2 BEEP
I
3 TCOM
I
4 TSTART
I
10 RESET
I
16 TXD
I
17 CWK
I
18 PTT
20 DRXD
I
21 DCLK
22 DTXD
I
23 HSK0
I
25 FULL
26 VSQL
27 GPRXD
29 EXTXD
30 EXRXD
32 BPST
33 RXD
34 TXD
35 CK
36 DT
42 RD
I
44 WR
46 CWST
I
I
47 TUMB
I
48 CS0
I
52–70 A16–A0
71 PWS
I
73 DSKY
I
74 SEND
I
75 MDA
I
76 MCK
I
77 ECK
78 ESIO
I
79–86 D7–D0
87 RXS
I
88 TXS
I
90 DCV
I
91 TEMP
I
92 KEYS
4-5
Description
a /MNGR] input.
/
Description
Beep audio.
Tuner Scan control signal to the automatic
antenna tuner.
Motor lock contol signal to the automatic
antenna tuner.
CPU reset signal.
L=The CPU is reset.
L-bus wakeup signal from the FRONT CPU.
L=Wakeup.
CW/FSK keing input.
L=Key down.
PTT input.
L=Pushed.
RX data from the DSP.
Serial clock to the DSP.
TX serial data to the DSP.
Hand shake signal to the DSP.
L=When the command is not granted.
ALE/SELCALL data full detect.
H=Data full.
Voice squelch detection.
L=Voice detected. (Squelch open)
GPS data (4800 bps).
External data output.
External data input.
Beep status detection.
H=Detected.
Data to the front CPU.
Data from the front CPU.
Serial clock to the DDS IC.
Serial data to/from the DDS IC.
SRAM data read control.
SRAM data write control.
CW status detection.
L=While transmitting in the CW mode.
Band switching control.
H= When the operating frequency is
13.3 MHz and higher.
SRAM chip select control.
L=Enabled.
SRAM control parallel bus.
Power supply line "14V" control.
H=During the transceiver's power is ON.
Keying output.
TX mute.
H=Mute.
Serial data to the D/A converter, shift reg-
ister and electronic volume.
Serial clock to the D/A converter, shift reg-
ister and electronic volume.
EEPROM serial clock.
EEPROM serial data.
SRAM control parallel bus.
RX power supply line control.
H=While receiving.
TX power supply line control.
H=While transmitting.
External power source detect.
TX power AMP temperature sensing volt-
age.
External tuner key control.
I/O
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I/O
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I/O
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