Dead Line Detection - ABB Relion 670 Series RES670 Technical Manual

1MRK 511 365-UUS A
13.2.7.3
Phasor measurement unit RES670 2.1 ANSI
Technical manual
DeltaIA
0
20 ms
DeltaIB
0
20 ms
DeltaIC
0
20 ms
DeltaVA
0
20 ms
DeltaVB
0
20 ms
DeltaVC
0
20 ms
ANSI12000165 V2 EN
Figure 129: Internal signals DeltaV or DeltaI and the corresponding output signals

Dead line detection

A simplified diagram for the functionality is found in figure 130. A dead phase condition
is indicated if both the voltage and the current in one phase is below their respective setting
values VDLDPU and IDLDPU. If at least one phase is considered to be dead the output
DLD1PH and the internal signal DeadLineDet1Ph is activated. If all three phases are
considered to be dead the output DLD3PH is activated
Secondary system supervision
intBlock
PU_DI
AND
AND
PU_DI_A
OR
PU_DI_B
AND
PU_DI_C
AND
PU_DV
AND
PU_DV_A
AND
OR OR
PU_DV_B
AND
PU_DV_B
AND
ANSI12000165-2-en.vsd
Section 13
371