Receive Signalling Circuits; Receive Signalling Paths - Motorola MCS 2000 Service Instructions Manual

Receive Signalling
Circuits
DISC
(DISCRIMINATOR AUDIO
FROM RF SECTION)
Alert Tone Circuits
follows a path identical to conventional receive audio, where it is filtered (300-
3 kHz) and deemphasis.
(Refer to Figure 7-5 for reference for the following sections)
The ASFIC (U0200) is used to filter and limit all received data. The data enters
the ASFIC at U0200-J7. Inside U0200 the data is filtered according to data type
(HS or LS), then it is limited to a 0-5 V digital level. The MDC and trunking
high speed data appear at U0200-G4, where it connects to the µP U0103-77,
software decoder, and U0104-B8, hardware decoder (see SLIC description
block for further details)
The low speed limited data output (PL, DPL, and trunking LS) appears at
U0200-A4, where it connects to the SLIC. While receiving low speed data, the
µP may output a sampling waveform, depending on the sampling technique,
to U0200-C3 of between 1 and 2 kHz.
The low speed data is read by the µP at twice the frequency of the sampling
waveform; a latch configuration in the ASFIC stores one bit every clock cycle.
The external capacitors C0211, C0212, and C0203 set the low frequency pole
for a zero crossings detector in the limiters for PL and HS data. The hysteresis
of these limiters is programmed based on the type of received data. Note that
during HS data the µP may generate a sampling waveform seen at U0200-G1.
G1
HIGH SPEED
CLOCK
DATA FILTER
LIMITER
AND DEEMPHASIS
J7
PL
ASFIC
IN
U0200
FILTER
LOW SPEED
LIM CAP
C5
Figure 7-5

Receive Signalling Paths

When the software determines that it needs to give the operator an audible
feedback (for a good key press, or for a bad key press), or radio status (trunked
system busy, phone call, circuit failures), it sends an alert tone to the speaker.
It does so by sending SPI BUS data to U0200 which sets up the audio path to
the speaker for alert tones. The alert tone itself can be generated in one of two
ways: internally by the ASFIC, or externally using the µP and the ASFIC.
C3
LOW SPEED
CLOCK
RX
G4
LIM OUT
PL A4
LIMITER
LIM
RX LIM
CAP
J3
Controller Section Theory of Operation
MICRO
CONTROLLER
7-25