Receive Signalling Circuits - Motorola GM328 Service Manual

Controller Board Audio and Signalling Circuits
2.5

Receive Signalling Circuits

Refer to 1-6 for reference for the following sections.
DET AUDIO
DISCRIMINATOR AUDIO
FROM RF SECTION
(IF IC)
2.5.1 Sub-audible (PL/DPL) and High Speed Data Decoder
The ASFIC CMP (U0221) is used to filter and limit all received data. The data enters the ASFIC
CMP at input DISC (U0221-2). Inside U0221 the data is filtered according to data type (HS or LS),
then it is limited to a 0-5V digital level. The MDC and trunking high speed data appear at U0221-19,
where it connects to the µP U0101-82
The low speed limited data output (PL, DPL, and trunking LS) appears at U0221-18, where it
connects to the µP U0101-80.
The low speed data is read by the µP at twice the frequency of the sampling waveform; a latch
configuration in the ASFIC CMP stores one bit every clock cycle. The external capacitors C0236,
and C0244 set the low frequency pole for a zero crossings detector in the limiters for PL and HS
data. The hysterisis of these limiters is programmed based on the type of received data.
2.5.2 Alert Tone Circuits
When the software determines that it needs to give the operator an audible feedback (for a good key
press, or for a bad key press), or radio status (trunked system busy, phone call, circuit failures), it
sends an alert tone to the speaker. It does so by sending SPI BUS data to U0221 which sets up the
audio path to the speaker for alert tones. The alert tone itself can be generated in one of two ways:
internally by the ASFIC CMP, or externally using the µP and the ASFIC CMP.
The allowable internal alert tones are 304, 608, 911, and 1823Hz. In this case a code contained
within the SPI BUS load to the ASFIC CMP sets up the path and determines the tone frequency, and
at what volume level to generate the tone. (It does not have to be related to the voice volume
setting).
For external alert tones, the µP can generate any tone within the 100-3000Hz audio band. This is
accomplished by the µP generating a square wave which enters the ASFIC CMP at U0221-19.
Inside the ASFIC CMP this signal is routed to the alert tone generator.
DATA FILTER
LIMITER
AND DEEMPHASIS
2 DISC
ASFIC_CMP
U0221
FILTER LIMITER
PLCAP2
PLCAP
25
8
Figure 1-6 Receive Signalling Paths
82
HSIO
19
CONTROLLER
44
80
LSIO
18
85
1-19
MICRO
U0101