Interfacing; Microprocessor Clock Synthesizer; Serial Peripheral Interface (Spi) - Motorola MCS 2000 Service Instructions Manual

Interfacing

Microprocessor
Clock Synthesizer
Serial Peripheral
Interface (SPI)
that is approximately equal to the voltage present at the inverting input
during the maximum current voltage drop through R5612.
PA control voltage limit consists of a portion of the control voltage fed back to
the power control loop. PA_CNTL_LIM is produced by a voltage divider
network on the PA board. When PA_CNTL_LIM goes above the reference
voltage of 4.65 V plus one diode voltage drop (i.e. 0.7 V) then protection
begins. At this point the control voltage PA_CNTL is clamped. This protects
the PA from being driven too hard by PA_CNTL which could cause excessively
high output power
(Refer to "Clock Distribution Block Diagram" on page 7-10, and Interface
schematic page 10-24 for general reference)
(Refer to ASFIC schematic page 10-23 for reference)
The clock source for the microprocessor system is generated by the ASFIC
(U0200). Upon power-up the reference oscillator U5800 (Pendulum) provides
a 16.8 MHz reference. Based on this reference the synthesizer (U5801)
generates a 2.1 MHz waveform that is routed from the RF section (via C0403)
to the ASFIC (on U0200-E1) and the option connectors (J0401-3 and J0408-3).
At the option connectors the 2.1 MHz may be used as a reference for any
option boards that are attached. For the main board controller the ASFIC uses
2.1 MHz as a reference input clock signal for its internal synthesizer. The
ASFIC, in addition to audio circuitry, has a programmable synthesizer which
can generate a synthesized signal ranging from 1200 Hz to 32.769 MHz in
1200 Hz steps.
When power is first applied, the ASFIC will generate its default 3.6864 MHz
CMOS square wave µ P CLK (on U0200-D1) and this is routed to the
microprocessor (U0103-36/U0003-E3) and SLIC (U0104-A3). After the
microprocessor starts operation, it reprograms the ASFIC clock synthesizer to
a higher µ P CLK frequency (usually 7.3728 or 14.7456 MHz) and continues
operation.
The ASFIC synthesizer loop uses C0208, C0209 and R0204 to set the switching
time and jitter of the clock output. If the synthesizer cannot generate the
required clock frequency it will switch back to its default 3.6864 MHz output.
Because the ASFIC synthesizer and the µ P system will not operate without the
2.1 MHz reference clock it (and the voltage regulators) should be checked first
in debugging the system.
(Refer to Controller schematic page 10-19 for reference)
The µ P communicates to many of the ICs through its SPI port. This port
consists of SPI TX DATA (U0103-66/U0003-B2), SPI RX DATA (U0103-65/
U0003-B1), CLK (U0103-67/U0003-A2) and chip select lines going to the
various ICs, connected on the SPI PORT (BUS). This BUS is a synchronous bus,
in that the timing clock signal CLK is sent while SPI data (SPI TX DATA or SPI
RX DATA) is sent. Therefore, whenever there is activity on either SPI TX DATA
or SPI RX DATA there should be a uniform signal on CLK. The SPI TX DATA is
used to send serial from a µ P to a device, and SPI RX DATA is used to send data
from a device to a µ P.
Controller Section Theory of Operation 7-9