Receive Signalling Circuits; Sub-Audible Data Decoder (Pl/Dpl); High Speed Data Decoder - Motorola GM950E Service Manual

7.0

Receive Signalling Circuits

Refer to Figure 6.3-4 for reference for the following sections.
DISCRIMINATOR AUDIO
FROM RF SECTION
7.1

Sub-audible Data Decoder (PL/DPL)

The receiver audio signal entering the AFIC U0103 at pin 8 first passes through the Tone PL filter or
the Digital PL filter, depending on the PL option selected for the current operating mode. Filtered PL
is then coupled to the PL detector circuit, with detected PL output at U0103-27. At this point the
signal will appear as a square wave version of the sub-audible signal which the radio received. The
microprocessor U0101-64 will decode the signal directly to determine if it is the tone / code which is
currently active on that mode.
7.2

High Speed Data Decoder

The unattenuated receiver audio signal from U0103-22 is AC coupled to the input of centre slicer
circuit U0105-2. The non-inverting input of Op-amp U0105-2 is fed through resistor R0162.
Capacitor C0164 sets a low-pass corner frequency of 3.3kHz. The inverting input of Op-amp U0105-
2 is fed through resistor R0163. Capacitor C0163 sets a low-pass corner frequency of 16Hz.
During operation, R0163 / C0163 establish an average DC offset level at U0105-2 pin 6 dependent
on the average DC level of the undetected signal to set the "trigger" threshold of U0105-2. R0162 /
C0164 provide high audio frequency roll-off to improve falsing immunity, but passes 600 or 1200
baud signals. The detected output from the centre slicer circuit is buffered and inverted by Q0161
and then coupled to the µP U0101-1 where algorithms perform the final decoding.
Theory of Operation
HIGH SPEED DATA
CENTRE SLICER
U0105-2
22
UNATTEN
RX OUT
PL
8
DPL
DET AUDIO
FILTER
IN
GEPD_5430
(IF IC)
DPL
25
Figure 6.3-4 Receive Signalling Path.
PL CLOCK
32
STROBE
AFIC
U0103
PL DPL 27
LIMITER
DECODER
OUT
TPL
24
Receive Signalling Circuits
1
57
MICRO
CONTROLLER
U0101
64
GEPD 5430
6.3-15