The Hips Chip Clock Tree - IBM RS/6000 SP Problem Determination Manual

This soft copy for use by IBM employees only.
Figure 50. The HiPS Chip Clock Tree
First, the clock is put through a delay tap. The delay tap breaks the clock into
eight phases, which are later used to tune the individual switch port. Each of the
eight phases is driven to each of the switch chips. You can see how switch chip
0, 1, 6, and 7 are all redriven from one source and chips 2, 3, 4, and 5 are
redriven from another. If you get failures trying to talk with all four chips on a
single branch, and the others look okay, you can be pretty sure that the cause is
the chip which redrives their clock.
Basically, when you get massive errors, look for patterns that match the clock
redrive patterns, and you may be able to quickly narrow down your culprit.
4.3.4 SP Switch Clock Subsystem
The TBS board supports the use of multiple clock sources:
jacks J19 to J33 are on a different branch. If none of the jacks have a clock,
then the problem most likely stems back to level A, or back to the clock card,
or even back to the switch that is supposed to be driving that clock card.
Now, if none of the even jacks (J4 through J18) have clocks on them, which
could be indicated by the diagnostics on all of the nodes connected to these
jacks, you can be pretty sure that is the B level redrive chip that has broken.
You can imagine the diagnostic power that you derive from knowing the
clock tree.
•
Two internal oscillators (attached to two of the board' s
• One of two possible external (HiPS-like) clock inputs:
−
To be used for a center of the room clock source, or "dual switch" clock
source, or both
−
Currently only one external connection is supported
101
Chapter 4. The Switch