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EOC
End of Conversion.
0
1
MUX
Single-ended/differential channel indicator.
0
1
INT
Data valid.
0
1
CN3 to CN0
If you trigger the A/D conversion by the on-board pacer, your software
should check the INT bit, not the EOC bit, before it reads the conver-
sion data.
EOC can equal 0 in two different situations: the conversion is
completed or no conversion has been started. Your software should
therefore wait for the signal INT = 1 before it reads the conversion
data. It should then clear the INT bit by writing any value to the A/D
status register BASE+8.
3 0
PCM-3718H/3718HG User's Manual
The A/D converter is idle, ready for the next conver-
sion. Data from the previous conversion is available
in the A/D data registers.
The A/D converter is busy, implying that the A/D
conversion is in progress.
8 differential channels
16 single-ended channels
No A/D conversion has been completed since the last
time the INT bit was cleared. Values in the A/D data
registers are not valid data.
The A/D conversion is completed, and converted data
is ready. If the INTE bit of the control register
(BASE+9) is set, an interrupt signal will be sent to the
PC bus through interrupt level IRQn, where n is
specified by bits I2, I1 and I0 of the control register.
Though the A/D status register is read-only, writing to
it with any value clears the INT bit.
When EOC = 0, these status bits contain the channel
number of the next channel to be converted.
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