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XTAL_IN
48 MHz
C
X
V
SSA
Figure 5. Placement of the Capacitors and Crystal
with Clock Signal Generated Internally
The crystal is a classical parallel resonance crystal of
48 MHz. The values of the capacitors C
manufacturer of the crystal. A typical value is 36 pF. The
crystal has to fulfill impedance characteristics specified in
the NCN49597data sheet. As an oscillator is sensitive and
precise, it is advised to put the crystal as close as possible on
the board and to ground the case.
XOUT
XOUT is the analog output pin of the oscillator. When the
clock signal is provided from an external generator, this
output must be floating. When working with a crystal, this
pin cannot be used directly as clock output because no
additional loading is allowed on the pin (limited voltage
swing).
TXD
TXD is the digital output of the asynchronous serial
communication (SCI) unit. Only half−duplex transmission
is supported. It is used to realize the communication between
the NCN49597and the application microcontroller. The
TXD is an open drain IO (5 V safe). External pull−up
resistances (typically 10 kW) are necessary to generate the
5 V level. See Figure 4 for the circuit schematic.
RXD
This is the digital input of the asynchronous SCI unit.
Only half−duplex transmission is supported. This pin
supports a 5 V level. It is used to realize the communication
between the NCN49597and the application microcontroller.
RXD is a 5 V safe input.
T_REQ
T_REQ is the transmission request input of the Serial
Communication Interface. When pulled low its initiate a
local communication from the application micro controller
to NCN49597. T_REQ is a 5 V safe input. See also
paragraph Error! Reference source not found..
BR1, BR0
BR0 and BR1 are digital input pins. They are used to select
the baud rate (bits/second) of the Serial Communication
Interface unit. The rate is defined according to Error!
Reference source not found.. The values are taken into
XTAL_OUT
PC20111118.1
C
X
are given by the
X
http://onsemi.com
NCN49597
account after a reset, hardware or software. Modification of
the baud rate during function is not possible. BR0 and BR1
are 5 V safe.
CRC
CRC is a 5 V compliant open drain output. An external
pull−up resistor defines the logic high level as illustrated in
Figure 4. A typical value for this pull−up resistance "R" is
10 kW. The signal on this output depends on the cyclic
redundancy code result of the received frame. If the cyclic
redundancy code is correct CRC = H during the pause
between two time slots.
RESB
RESB is a digital input pin. It is used to perform a
hardware reset of the NCN49597. This pin supports a 5 V
voltage level. The reset is active when the signal is low
(0 V).
TEST
TEST is a digital input pin with internal pull down resistor
used to enable the Hardware Test Mode of the chip. When
TEST is left open or forced to ground Normal Mode is
enabled. When TEST is forced to VDD the Hardware Test
Mode is enabled. This mode is used during production test
of the IC and will not be described here. TEST pin is not 5 V
safe.
TX_ENB
TX_ENB is a digital output pin. It is low when the
transmitter is activated. The signal is available to turn on the
line driver. TX_ENB is a 5 V safe with open drain output,
hence a pull−up resistance is necessary achieve the
requested voltage level associated with a logical one. See
also Figure 4 for reference.
TX_OUT
TX_OUT is the analog output pin of the transmitter. The
provided signal is the S−FSK modulated frames. A filtering
operation must be performed to reduce the second and third
order harmonic distortion. For this purpose an active filter
is suggested. See also paragraph Transmitter Output
TX_OUT.
ALC_IN
ALC_IN is the automatic level control analog input pin.
The signal is used to adjust the level of the transmitted
signal. The signal level adaptation is based on the AC
component. The DC level on the ALC_IN pin is fixed
internally to 1.65 V. Comparing the peak voltage of the AC
signal with two internal thresholds does the adaptation of the
gain. Low threshold is fixed to 0.4 V. A value under this
threshold will result in an increase of the gain. The high
threshold is fixed to 0.6 V. A value over this threshold will
result in a decrease of the gain. A serial capacitance is used
to block the DC components. The level adaptation is
performed during the transmission of the first two bits of a
new frame. Eight successive adaptations are performed. See
7
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