ON Semiconductor NCN49597 Manual page 21

FRAME_CLK: is active at counter values 0 and inactive at
all other counter values. This signal is used to indicate the
transmission or reception of a new frame.
PRE_BYTE_CLK is a signal which is 8 CHIP_CLK
sooner than BYTE_CLK. This signal is used as an interrupt
for the internal microcontroller and indicates that a new byte
for transmission must be generated.
PRE_FRAME_CLK is a signal which is 8 CHIP_CLK
sooner than FRAME_CLK. This signal is used as an
interrupt for the internal microcontroller and indicates that
a new frame will start at the next FRAME_CLK.
PRE_SLOT is logic 1 between the rising edge of
PRE_FRAME_CLK and the rising edge of FRAME_CLK.
This signal can be provided at the digital output pin
TXD/PRES when R_CONF[7] = 0 (See paragraph Local
Port and Error! Reference source not found., field
Transmitter(S− FSK Modulator )
TX_EN
ALC_IN
TX_OUT
ARM Interface and Control
The interface with the ARM consists in a 8−bit data
registers R_TX_DATA, 2 control registers R_TX_CTRL
and R_ALC_CTRL, a flag TX_RXB defining transmit and
receive and 2 16−bit wide frequency step registers R_FM
and R_FS defining f (mark frequency = data 1) and f
M
(space frequency = data 0). All these registers are memory
mapped. Some of them are for internal use only and cannot
be accessed by the user.
Processing of the physical frame (preamble, MAC
address, CRC) is done by the ARM.
Table 20. FS AND FM STEP REGISTERS
ARM Register
R_FS[15:0]
R_FM[15:0]
NCN49597
ALC
control
LP
D/A
Filter
Figure 15. Transmitter Block Diagram
S
Hard Reset Soft Reset
0000h 0000h
0000h 0000h
http://onsemi.com
R_CONF_TXD_PRES_SEL
host controller to synchronize its software with the
FRAME_CLK of NCN49597.
Transmitter Path Description (S−FSK Modulator)
For the generation of the space and mark frequencies, the
direct digital synthesis (DDS) of the sine wave signals is
performed under the control of the microprocessor. After a
signal conditioning step, a digital to analog conversion is
performed. As for the receive path, a sigma delta modulation
technique is used. In the analog domain, the signal is low
pass filtered, in order to remove the high frequency
quantization noise, and passed to the automatic level
controller (ALC) block, where the level of the transmitted
signal can be adjusted. The determination of the signal level
is done through the sense circuitry.
Transmit Data
& Sine Synthesizer
f f f f
MI MQ SI SQ
TO RECEIVER
Sine Wave Generator
A sine wave is generated with a direct digital synthesizer
DDS. The synthesizer generates in transmission mode a sine
wave either for the space frequency (f
mark frequency (f , data1). In reception the synthesizer
M
generates the sine and cosine waves for the mixing process,
f , f , f , f (space and mark signals in phase and
SI SQ MI MQ
quadrature). The space and mark frequencies are defined in
an individual step 16 bit wide register.
Step register for the space frequency f
Step register for the mark frequency f
21
) and can be used by the external
ARM
Interface
&
Control
PC20091019.1
, data 0) or for the
S
Description
S
M