Detailed Pin Description - ON Semiconductor NCN49597 Manual

Table 4. NCN49597QFN PIN FUNCTION DESCRIPTION
Pin No. Pin Name
16 TXD/PRES
17 XIN
18 XOUT
19 VDD1V8
20 VSS
21 VDD
22 TXD
24 RXD
25 SCK
26 SDI
27 SDO
28 CSB
29 T_REQ
30 SEN
31 BR1
32 BR0
33 CRC
35 RESB
36 TEST
37 TX_ENB
42 TX_OUT
43 ALC_IN
46 VDDA
47 VSSA
48 RX_OUT
49 RX_IN
51 REF_OUT
2, 38..41, 44, NC
45,50, 52
P: Power pin
A: Analog pin
D: Digital pin

Detailed Pin Description

VDDA
VDDA is the positive analog supply pin. Nominal voltage
is 3.3 V. A ceramic decoupling capacitor C
be placed between this pin and the VSSA. Connection path
of this capacitance to the VSSA on the PCB should be kept
as short as possible in order to minimize the serial resistance.
NCN49597
I/O Type
Out D, 5V Safe
In A
Out A
P
P
P
Out D, 5V Safe
In D, 5V Safe
Out D
In D
Out D
In D
In D, 5V Safe
In D
In D, 5V Safe
In D, 5V Safe
Out D, 5V Safe
In D, 5V Safe
In D
Out D, 5V Safe
Out A
In A
P
P
Out A
In A
Out A
5V Safe:
REF_OUT
REF_OUT is the analog output pin which provides the
= 100 nF must voltage reference used by the A/D converter. This pin must
DA
be decoupled to the analog ground by a 1 mF ceramic
capacitance C
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5
Description
Output of transmitted data (TXD) or PRE_SLOT signal
(PRES)
Xtal input (can be driven by an internal clock)
Xtal output (output floating when XIN driven by external
clock)
1V8 regulator output. Foresee a decoupling capacitor
Digital ground
3.3V digital supply
SCI transmit output (open drain)
SCI receive input (Schmitt trigger output)
SPI interface external Flash
SPI interface external Flash
SPI interface external Flash
SPI interface external Flash
Transmit Request input
Boot option
SCI baud rate selection
SCI baud rate selection
Correct frame CRC indication (open drain output)
Master reset bar (Schmitt trigger input, active low)
Hardware Test enable (internal pull down)
TX enable bar (open drain)
Transmitter output
Automatic level control input
3.3V analog supply
Analog ground
Output of receiver low noise operational amplifier
Positive input of receiver low noise operational amplifier
Reference output for stabilization
Pins 2, 38..41, 44, 45, 50, 52 are not connected. These
pins need to be left open or connected to the GND plane.
IO that support the presence of 5V on bus line
Out: Output signal
In: Input signal
. The connection path of this capacitor to
DREF