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V
MAINS
VIR
VIF
ZeroCross
Figure 11. Zero Cross Detector Signals and Timing (example for 50 Hz)
50/60 Hz PLL
The output of the zero cross detector is used as an input for
a PLL. The PLL generates the clock CHIP_CLK which is 8
times the bit rate and which is in phase with the rising edge
Table 18. CHIP_CLK IN FUNCTION OF SELECTED BAUD RATE AND MAINS FREQUENCY
BAUD[1:0]
00
01
10
11
00
01
10
11
In case no zero crossings are detected the PLL freezes its internal timers in order to maintain the CHIP_CLK timing.
ZC _IN
ZC _IN
t
ZCD
MAINS_FREQ
50 Hz
60 Hz
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t
DEBOUNCE
10 ms
crossings. The PLL locks on the zero cross from negative to
positive phase. The bit rate is always an even multiple of the
mains frequency, so following combinations are possible:
Baudrate
300
600
1200
2400
360
720
1440
2880
18
t
= 0,5 .. 1 ms
PC20090620 .1
CHIP_CLK
2400 Hz
4800 Hz
9600 Hz
19200 Hz
2880 Hz
5760 Hz
11520 Hz
23040 Hz
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