Frequency (Hz) - ON Semiconductor NCN49597 Manual

Power line carrier modem
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decreases the voltage level of 230 Vrms at the mains
frequency well below the sensitivity of the NCN49597.
T
20
−20
−60
−100
−140
10
Table 22. VALUE OF THE RESISTORS AND CAPACITORS
Remark: The analog part of NCN49597 is referenced to the
internal analog ground REF_OUT = 1.65 V (typical value).
If the external circuitry works with a different analogue
reference level one must be sure to place a decoupling
capacitor.
Auto Gain Control (AGC)
The receiver path has a gain stage which is used for
automatic gain control. The gain can be changed in 8 steps
of 6 dB. The control of the AGC is done by a digital circuit
which measures the signal level after the AD converter, and
regulates the average signal in a window around a
percentage of the full scale. The AGC works in 2 cycles: a
measurement cycle at the rising edge of the CHIP_CLK and
an update cycle starting at the next CHIP_CLK.
Low Noise Anti Aliasing Filter
rd
The receiver has a 3
order continuous time low pass filter
in the signal path. This filter is in fact the same block as in
the transmit path which can be shared because
NCN49597
100
Figure 21. Transfer Function of 50 Hz Suppression Circuit
Component
C
1
C
2
C
DREF
R
1
R
2
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1k

Frequency (Hz)

NCN49597works in half duplex mode. The typical corner
frequency f
= 138 kHz and is internally trimmed to
−3dB
compensate for process variation.
A/D Converter
The output of the low pass filter is input for an analog 4
order sigma−delta converter. The DAC reference levels are
supplied from the reference block. The digital output of the
converter is fed into a noise shaping circuit blocking the
quantization noise from the band of interest, followed by a
decimation and a compensation step.
Quadrature Demodulator
The quadrature demodulation block takes the AD signal
and mixes it with the in−phase and quadrature phase of the
f
and f
carrier frequencies. After a low pass filter and
S
M
rectification the mixer output signals are further processed
in software. There the accumulation over a period of
CHIP_CLK is done which results in the discrimination of
data 0 and data 1.
25
10k
100k
Value
1.5
1.5
1
22
11
Unit
nF
nF
mF
kW
kW
th

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