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the VSSA on the PCB should be kept as short as possible in
order to minimize the serial resistance.
VSSA
VSSA is the analog ground supply pin.
VDD
VDD is the 3.3 V digital supply pin. A ceramic decoupling
capacitor C
= 100 nF must be placed between this pin and
DD
the VSS. Connection path of this capacitance to the VSS on
the PCB should be kept as short as possible in order to
minimize the serial resistance.
VSS
VSS is the digital ground supply pin.
Figure 3: Recommended Layout of the Placement of
Decoupling Capacitors
VDD1V8
This is an additional power supply pin to decouple an
internal LDO regulator. The decoupling capacitor should be
placed as close as possible to this output pin as illustrated in
Figure 4.
RX_OUT
RX_OUT is the output analog pin of the receiver low
noise input op−amp. This op−amp is in a negative feedback
configuration.
RX_IN
RX_IN is the positive analog input pin of the receiver low
noise input op−amp. Together with RX_OUT and
REF_OUT, an active high pass filter is realized. This filter
removes the main frequency (50 or 60 Hz) from the received
signal. The filter characteristics are determined by external
capacitors and resistors. A typical application schematic can
be found in paragraph 50/60 Hz Suppression Filter.
ZC_IN
ZC_IN is the mains frequency analog input pin. The signal
is used to detect the zero cross of the 50 or 60 Hz sine wave.
NCN49597
This information is used, after filtering with the internal
PLL, to synchronize frames with the mains frequency. In
case of direct connection to the mains it is advised to use a
series resistor of 1 MW in combination with two external
clamp diodes in order to limit the current flowing through
the internal protection diodes.
RX_DATA
RX_DATA is a 5 V compliant open drain output. An
external pull−up resistor defines the logic high level as
illustrated in Figure 4. A typical value for the pull−up
resistance "R" is 10 kW. The signal on this output depends
on the status of the data reception. If NCN49597waits for
configuration RX_DATA outputs a pulse train with a 10 Hz
frequency. After Synchronization Confirm Time out
RX_DATA
synchronization RX_DATA = 1.
PC20090722. 2
Figure 4. Representation of 5V Safe Output
TDO, TDI, TCK, TMS, and TRSTB
All these pins are part of the JTAG bus interface. The
JTAG interface is used during production test of the IC and
will not be described here. Input pins (TDI, TCK, TMS, and
TRSTB) contain internal pull−down resistance. TDO is an
output. When not used, the JTAG interface pins may be left
floating.
TXD/PRES
TXD/PRES is the output for either the transmitting data
(TX_DATA) or a synchronization signal with the time−slots
(PRE_SLOT). TXD/PRES. More information can be found
in paragraph Local Port.
XIN
XIN is the analog input pin of the oscillator. It is connected
to the interval oscillator inverter gain stage. The clock signal
can be created either internally with the external crystal and
two capacitors or by connecting an external clock signal to
XIN. For the internal generation case, the two external
capacitors and crystal are placed as shown in Figure 5. For
the external clock connection, the signal is connected to XIN
and XOUT is left unused.
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