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NCN49597
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Power Line Carrier Modem
ON Semiconductor's NCN49597 is an IEC 61334−5−1 compliant
power line carrier modem using spread−FSK (S−FSK) modulation for
robust low data rate communication over power lines. NCN49597 is
built around an ARM processor core, and includes the MAC layer.
With this robust modulation technique, signals on the power lines can
pass long distances. The half−duplex operation is automatically
synchronized to the mains, and can be up to 4800 bits/sec.
The product configuration is done via its serial interface, which
allows the user to concentrate on the development of the application.
The NCN49597 is implemented in ON Semiconductor mixed signal
technology, combining both analog circuitry and digital functionality
on the same IC.
Features
•
Power Line Carrier Modem for 50 and 60 Hz Mains
•
Fully compliant to IEC 61334−5−1 and CENELEC EN 50065−1
•
Complete Handling of Protocol Layers Physical to MAC
•
Programmable Carrier Frequencies in CENELEC A-Band from 9 to
95 kHz; B−Band from 95 to 125 kHz, in 10 Hz Steps
•
Half Duplex
•
Data Rate Selectable:
300 – 600 – 1200 − 2400 – 4800 baud (@ 50 Hz)
360 – 720 – 1440 − 2880 – 5760 baud (@ 60 Hz)
•
Synchronization on Mains
•
Repetition Algorithm Boost the Robustness of Communication
•
SCI Port to Application Microcontroller
•
SCI Baudrate Selectable: 9.6 – 19.2 – 38.4 − 115.2 kb
•
Power Supply 3.3 V
•
Ambient Temperature Range: −40°C to +80°C
•
These Devices are Pb−Free and are RoHS Compliant*
Typical Applications
•
ARM: Automated Remote Meter Reading
•
Remote Security Control
•
Streetlight Control
•
Transmission of Alerts (Fire, Gas Leak, Water Leak)
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2011
December, 2011 − Rev. P0
MARKING DIAGRAMS
XXXX
Y
ZZ
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 27 of this data sheet.
1
http://onsemi.com
1
52
QFN52 8x8, 0.5P
CASE 485M
52
1
ARM
ON
XXXXYZZ
NCN 49597
C597−901
e
3
= Date Code
= Plant Identifier
= Traceability Code
Publication Order Number:
NCN49597/D
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Table of Contents
Summary of Contents for ON Semiconductor NCN49597
- Page 1 Power Line Carrier Modem ON Semiconductor’s NCN49597 is an IEC 61334−5−1 compliant power line carrier modem using spread−FSK (S−FSK) modulation for robust low data rate communication over power lines. NCN49597 is http://onsemi.com built around an ARM processor core, and includes the MAC layer.
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Page 2: Application Example
Figure 1 shows an S−FSK PLC modem build around The filter components are tuned for a space and mark NCN49597. For synchronization the line frequency is frequency of 63.3 and 74 kHz respectively. The output of the coupled in via a 1 MW resistor. The Schottky diode pair D... - Page 3 NCN49597 Table 1. EXTERNAL COMPONENTS LIST AND DESCRIPTION Component Function − Remark Typ Value Tolerance Unit High Voltage coupling capacitor; 630 V ±20% Zero Cross noise suppression ±20% X−tal load capacitor ±20% Decoupling block capacitor 1.8 V internal supply −20 +80% High pass receive filter ±1%...
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Page 4: Normal Operating Conditions
QFN Packaging M50Hz_IN TX_EN TEST IO11 IO0/RX_DATA AMIS49597 T_REQ TRST Figure 2. QFN Pin−out of NCN49597 (Top view) Table 4. NCN49597QFN PIN FUNCTION DESCRIPTION Pin No. Pin Name Type Description ZC_IN 50/60 Hz input for mains zero cross detection 3..5, 12..15, IO3 .. -
Page 5: Detailed Pin Description
NCN49597 Table 4. NCN49597QFN PIN FUNCTION DESCRIPTION Pin No. Pin Name Type Description TXD/PRES D, 5V Safe Output of transmitted data (TXD) or PRE_SLOT signal (PRES) Xtal input (can be driven by an internal clock) XOUT Xtal output (output floating when XIN driven by external... - Page 6 NCN49597 the VSSA on the PCB should be kept as short as possible in This information is used, after filtering with the internal order to minimize the serial resistance. PLL, to synchronize frames with the mains frequency. In case of direct connection to the mains it is advised to use a...
- Page 7 Clock Signal Generated Internally RESB is a digital input pin. It is used to perform a hardware reset of the NCN49597. This pin supports a 5 V The crystal is a classical parallel resonance crystal of voltage level. The reset is active when the signal is low 48 MHz.
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Page 8: Electrical Characteristics
NCN49597 also paragraph Amplifier with Automatic Level Control SCK, SDI, SDO, CSB These signals from the SPI interface to an optional (ALC). external Flash. See Reference 1. ELECTRICAL CHARACTERISTICS DC and AC Characteristics Oscillator: Pin XIN, XOUT In production the actual oscillation of the oscillator and duty cycle will not be tested. The production test will be based on the static parameters and the inversion from XIN to XOUT in order to guarantee the functionality of the oscillator. - Page 9 NCN49597 Zero Cross Detector and 50/60 Hz PLL: Pin ZC_IN Table 6. ZERO CROSS DETECTOR AND 50/60 HZ PLL Parameter Test Conditions Symbol Unit Maximum peak input current −20 ZC_IN Maximum average input current During 1 ms Imavg −2 ZC_IN...
- Page 10 NCN49597 Transmitter External Parameters: Pin TX_OUT, ALC_IN, TX_ENB To guarantee the transmitter external specifications the TX_CLK frequency must be 12 MHz ± 100 ppm. Table 7. TRANSMITTER EXTERNAL PARAMETERS Parameter Test Conditions Symbol Unit Maximum peak output level = 23 – 75 kHz 0.85...
- Page 11 NCN49597 Receiver External Parameters: Pin RX_IN, RX_OUT, REF_OUT Table 9. RECEIVER EXTERNAL PARAMETERS Parameter Test Conditions Symbol Unit Input offset voltage 42 dB AGC gain = 42 dB OFFS_RX_IN Input offset voltage 0 dB AGC gain = 0 dB OFFS_RX_IN Max.
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Page 12: Power−On−Reset (Por)
NCN49597 Power−on−Reset (POR) Table 11. POWER−ON−RESET Parameter Test Conditions Symbol Unit POR threshold Power supply rise time 0 to 3V RPOR Digital Outputs: TDO, CLK_OUT Table 12. DIGITAL OUTPUTS: TDO, CLK_OUT Parameter Test Conditions Symbol Unit Low output voltage = 4 mA... -
Page 13: General Description
The frequency pairs supported by the development of applications. The user just needs to send the NCN49597 are in the range of 9 − 150 kHz with a typical raw data to the NCN49597 and no longer has to take care of separation of 10 kHz. - Page 14 Major User Type Minor User Type PC201111 12.2 Figure 6. Application Examples • NCN49597 is intended to connect equipment using Minor type: Distribution Line Carrier (DLC) communication. It serves Spy or Monitor: ♦ two major and two minor types of applications: Spy or Monitor mode is used to only listen to the •...
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Page 15: Functional Description
NCN49597 Functional Description The block diagram below represents the main functional units of the NCN49597: VDD1V8 Transmitter (S− FSK Modulator) Communication Controller TX_ENB Transmit Data Serial TX_OUT TO Power Amplifier TO Application Filter & Sine Synthesizer Comm. T_REQ Micro Controller... -
Page 16: Detailed Hardware Description
PLC communication. RX_DATA TIMER, and the Power on reset. The processor uses the indicates if Receiving is in progress, or if NCN49597 is ARM Reduced Instruction Set Computer (RISC) waiting for synchronization, or of it configures. CRC architecture optimized for IO handling. - Page 17 NCN49597 Clock and Control Zero Clock Generator CHIP_CLK ZC_IN crossing & Timer XOUT PC20090619.4 Figure 9. Clock and Control Block Zero Cross Detector case of direct connection to the mains it is advised to use a ZC_IN is the mains frequency analog input pin. The signal series resistor of 1 MW in combination with two external is used to detect the zero cross of the 50 or 60 Hz sine wave.
- Page 18 NCN49597 MAINS ZC _IN ZC _IN ZeroCross = 0,5 .. 1 ms DEBOUNCE 10 ms PC20090620 .1 Figure 11. Zero Cross Detector Signals and Timing (example for 50 Hz) 50/60 Hz PLL crossings. The PLL locks on the zero cross from negative to The output of the zero cross detector is used as an input for positive phase.
- Page 19 NCN49597 MAINS ZC _IN 6 bit @ 300 baud ZeroCross PLL in lock CHIP _CLK Start of Physical PreFrame 10 ms PC 20090 619 .3 *The start of the Physical Subframe is shifted back with R_ZC_ADJUST[7:0] x 26 mS = t to compensate for the zero cross delay.
- Page 20 The timing generator is the same for transmit and receive For correct functionality the external circuit illustrated in mode. When NCN49597 switches from receive to transmit Figure 13 must be connected to the oscillator pins. For a and back from transmit to receive, the R_CHIP_CNT...
- Page 21 This signal is used to indicate the host controller to synchronize its software with the transmission or reception of a new frame. FRAME_CLK of NCN49597. PRE_BYTE_CLK is a signal which is 8 CHIP_CLK Transmitter Path Description (S−FSK Modulator) sooner than BYTE_CLK.
- Page 22 Or the content of both R_FS[15:0] and R_FM[15:0] are TX_ENB to enable the external power amplifier. TX_ENB defined as: is 1 when the NCN49597 is in receive mode. TX_ENB is 0 • R_FS[15:0]_dec = Round(2 when NCN49597is in transmit mode. When going from •...
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Page 23: Receiver Path Description
Therefore NCN49597 has a low noise operational DSP, as well the handling of the bits and the frames. amplifier at the input stage which can be used to make a high... -
Page 24: Quadrature Demodulator
Figure 19. Digital Path of the Receiver ADC and Quadrature Demodulation 50/60 Hz Suppression Filter noise operational amplifier. REF_OUT is the analog output NCN49597 receiver input provides a low noise input pin which provides the voltage reference (1.65 V) used by operational amplifier in a follower configuration which can the A/D converter. -
Page 25: Frequency (Hz)
Component Value Unit DREF Remark: The analog part of NCN49597 is referenced to the NCN49597works in half duplex mode. The typical corner internal analog ground REF_OUT = 1.65 V (typical value). frequency f = 138 kHz and is internally trimmed to −3dB... -
Page 26: Communication Controller
NCN49597 Bit Sync cross detector and loop delay in the Rx−filter circuitry will At the transmit side the data−stream is in sync and in phase cause a shift between the physical transmitted bit and the with the zero crossing of the mains. The complex impedance received S−FSK signal as illustrated in Figure 23. - Page 27 Control PC20091111.1 Figure 24. Communication Controller REFERENCE In this document references are made to: 4. DLMS UA 1000−2 Ed. 7.0 DLMS/COSEM 1. Design Manual NCN49597 Architecture and Protocols http://www.onsemi.com http://www.dlms.com/documentation/dlmsuacolou 2. EN 50065−1: Signaling on low−voltage electrical redbookspasswordprotectedarea/index.html installations in the frequency range 3 kHz to 5.
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Page 28: Package Dimensions
PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada Order Literature: http://www.onsemi.com/orderlit P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada...