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V
MAINS
VIR
ZC _IN
ZeroCross
CHIP _CLK
*The start of the Physical Subframe is shifted back with R_ZC_ADJUST[7:0] x 26 mS = t
Figure 12. Zero Cross Adjustment to Compensate for Zero Cross Delay (example for 50 Hz)
The phase difference between the zero cross of the mains
and CHIP_CLK can be tuned. This opens the possibility to
compensate for external delay t
for the 1.9 V positive threshold VIR
detector. This is done by pre−loading the PLL counter with
Table 19. ZERO CROSS DELAY COMPENSATION
R_ZC_ADJUST[7:0]
Oscillator
The oscillator works with a standard parallel resonance
crystal of 48 MHz. XIN is the input to the oscillator inverter
gain stage and XOUT is the output.
t
ZCD
PLL in lock
Start of Physical PreFrame
(e.g. opto coupler) and
ZCD
of the zero cross
ZC_IN
0000 0000
0000 0001
0000 0010
0000 0011
...
1111 1101
1111 1110
1111 1111
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NCN49597
(*)
10 ms
to compensate for the zero cross delay.
ZCD
a number value stored in register R_ZC_ADJUST[7:0]. The
adjustment period or granularity is 26 ms. The maximum
adjustment is 255 x 26 ms = 6.6 ms which corresponds with
1/3rd of the 50 Hz mains sine period.
19
t
6 bit @ 300 baud
PC 20090 619 .3
Compensation
0 ms
26 ms
52 ms
78 ms
...
6589 ms
6615 ms
6641 ms
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