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Current Consumption
Table 17. CURRENT CONSUMPTION
Parameter
Current consumption in receive
mode
Current consumption in transmit
mode
Current consumption when RESB
= 0
15. f
= 48 MHz.
CLK
General Description
The NCN49597 is a single chip half duplex S−FSK
modem dedicated to power line carrier (PLC) data
transmission on low− or medium−voltage power lines. The
device offers complete handling of the protocol layers from
the physical up to the MAC. NCN49597 complies with the
CENELEC EMC standard EN 50065−1 and the
IEC 61334−5−1 standards. It operates from a single 3.3 V
power supply and is interfaced to the power line by an
external power driver and transformer. An internal PLL is
locked to the mains frequency and is used to synchronize the
data transmission at data rates of 300, 600, 1200, 2400 and
4800 baud for a 50 Hz mains frequency, or 360, 720, 1440,
2880 and 5760 baud for a 60 Hz mains frequency. In both
cases this corresponds to 3, 6, 12 or 24 data bits per half cycle
of the mains period.
S−FSK is a modulation and demodulation technique that
combines some of the advantages of a classical spread
spectrum system (e.g. immunity against narrow band
interferers) with the advantages of the classical FSK system
(low complexity). The transmitter assigns the space
frequency f
to "data 0" and the mark frequency f
S
"data 1". The difference between S−FSK and the classical
FSK lies in the fact that f
S
each other, making their transmission quality independent
from each other (the strengths of the small interferences and
the signal attenuation are both independent at the two
frequencies). The frequency pairs supported by the
NCN49597 are in the range of 9 − 150 kHz with a typical
separation of 10 kHz.
The conditioning and conversion of the signal is
performed at the analog front−end of the circuit. The further
processing of the signal and the handling of the protocol is
Test Conditions
Current through V
and V
DD
(Note 15)
Current through V
and V
DD
(Note 15)
Current through V
and V
DD
(Note 15)
INTRODUCTION
and f
are now placed far from
M
http://onsemi.com
NCN49597
Symbol
I
DDA
RX
I
DDA
TX
I
DDA
RESET
digital. At the back−end side, the interface to the application
is done through a serial interface. The digital processing of
the signal is partitioned between hardwired blocks and a
microprocessor block. The microprocessor is controlled by
firmware. Where timing is most critical, the functions are
implemented with dedicated hardware. For the functions
where the timing is less critical, typically the higher level
functions, the circuit makes use of the ARM microprocessor
core.
The processor runs DSP algorithms and, at the same time,
handles the communication protocol. The communication
protocol, in this application, contains the MAC = Medium
Access Control Layer. The program running on the
microprocessor is stored into ROM. The working data
necessary for the processing is stored in an internal RAM. At
the back−end side the link to the application hardware is
provided by a Serial Communication Interface (SCI). The
SCI is an easy to use serial interface, which allows
communication between an external processor used for the
application software and the NCN49597 modem. The SCI
works on two wires: TXD and RXD. Baud rate is
to
programmed by setting 2 bits (BR0, BR1).
M
Because the low protocol layers are handled in the circuit,
the NCN49597 provides an innovative architectural split.
Thanks to this, the user has the benefit of a higher level
interface of the link to the PLC medium. Compared to an
interface at the physical level, the NCN49597 allows faster
development of applications. The user just needs to send the
raw data to the NCN49597 and no longer has to take care of
the protocol detail of the transmission over the specific
medium. This last part represents usually 50% of the
software development costs.
13
Min
Typ
Max
60
80
60
80
4
Unit
mA
mA
mA
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