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Figure 8. Data Stream is in Sync with Zero Cross of the Mains (example for 50 Hz)
Communication Controller
The Communication Controller block includes the
micro−processor, its peripherals: RAM, ROM, UART,
TIMER, and the Power on reset. The processor uses the
ARM Reduced Instruction Set Computer (RISC)
architecture optimized for IO handling. For most of the
instructions, the machine is able to perform one instruction
per clock cycle. The microcontroller contains the necessary
hardware to implement interrupt mechanisms, timers and is
able to perform byte multiplication over one instruction
cycle. The microcontroller is programmed to handle the
physical layer (chip synchronization), and the MAC layer
conform to IEC 61334−5−1. The program is stored in a
masked ROM. The RAM contains the necessary space to
store the working data. The back−end interface is done
through the Serial Communication Interface block. This
back−end is used for data transmission with the application
micro controller (containing the application layer for
concentrator, power meter, or other functions) and for the
definition of the modem configuration.
Clock and Control
According to the IEC 61334−5−1 standard, the frame data
is transmitted at the zero cross of the mains voltage. In order
to recover the information at the zero cross, a zero cross
detection of the mains is performed. A phase−locked loop
(PLL) structure is used in order to allow a more reliable
reconstruction of the synchronization. The output of this
NCN49597
20 ms
Local Port
actual status of the PLC communication. RX_DATA
indicates if Receiving is in progress, or if NCN49597 is
waiting for synchronization, or of it configures. CRC
indicates if the received frames are valid (CRC = OK).
TXD/PRES is the output for either the transmitting data
(TX_DATA) or a synchronization signal with the time−slots
(PRE_SLOT).
Serial Communication Interface
serial link using a receiving input (RxD) and a transmitting
output (TxD). The input port T_REQ is used to manage the
local communication with the application micro controller
and the baud rate can be selected depending on the status of
two inputs BR0, BR1. These two inputs are taken in account
after an NCN49597 reset. Thus when the application micro
controller wants to change the baud rate, it has to set the two
inputs and then provoke a reset.
DETAILED HARDWARE DESCRIPTION
block is the clock signal CHIP_CLK, 8 times over sampled
with the bit rate. The oscillator makes use of precise 48 MHz
quartz. This clock signal together with CHIP_CLK is fed
into the Clock Generator and time block. Here several
internal clock signals and timings are obtained by the use of
a programmed division scheme.
http://onsemi.com
16
t
48 bit @ 2400 baud
The controller uses 3 output ports to inform about the
The local communication is a half duplex asynchronous
PC20100609.1
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